M28LV64 データシートの表示（PDF） - STMicroelectronics

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M28LV64

64K (8K x 8) LOW VOLTAGE PARALLEL EEPROM with SOFTWARE DATA PROTECTION

STMicroelectronics 

M28LV64

Microcontroller Control Interface

The M28LV64 provides two write operation status

bits and one status pin that can be used to minimize

the system write cycle. These signals are available

on the I/O port bits DQ7 or DQ6 of the memory

during programming cycle only, or as the RB signal

on a separate pin.

Figure 4. Status Bit Assignment

DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0

DP TB PLTS Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z

DP = Data Polling

TB = Toggle Bit

PLTS = Page Load Timer Status

Data Polling bit (DQ7). During the internal write

cycle, any attempt to read the last byte written will

produce on DQ7 the complementary value of the

previously latched bit. Once the write cycle is fin-

ished the true logic value appears on DQ7 in the

read cycle.

Toggle bit (DQ6). The M28LV64 offers another

way for determining when the internal write cycle

is completed. During the internal Erase/Write cycle,

DQ6 will toggle from ”0” to ”1” and ”1” to ”0” (the

first read value is ”0”) on subsequent attempts to

read the memory. When the internal cycle is com-

pleted the toggling will stop and the device will be

accessible for a new Read or Write operation.

Page Load Timer Status bit (DQ5). In the Page

Write mode data may be latched by E or W up to

100µs after the previous byte. Up to 64 bytes may

be input. The Data output (DQ5) indicates the

status of the internal Page Load Timer. DQ5 may

be read by asserting Output Enable Low (tPLTS).

DQ5 Low indicates the timer is running, High indi-

cates time-out after which the write cycle will start

and no new data may be input.

Ready/Busy pin (available only on the

M28LV64). The RB pin provides a signal at its open

drain output which is low during the erase/write

cycle, but which is released at the completionof the

programming cycle.

Software Data Protection

The M28LV64 offers a software controlled write

protection facility that allows the user to inhibit all

write modes to the device including the Chip Erase

instruction. This can be useful in protecting the

memory from inadvertent write cycles that may

occur due to uncontrolled bus conditions.

The M28LV64is shipped as standard in the ”unpro-

tected” state meaning that the memory contents

can be changed as required by the user. After the

Software Data Protection enable algorithm is is-

sued, the device enters the ”Protect Mode” of

operation where no further write commands have

any effect on the memory contents. The device

remains in this mode until a valid Software Data

Protection (SDP) disable sequence is received

whereby the device reverts to its ”unprotected”

state. The Software Data Protection is fully non-

volatile and is not changed by power on/off se-

quences.

To enable the Software Data Protection (SDP) the

device requires the user to write (with a Page Write)

three specific data bytes to three specific memory

locations as per Figure 5. Similarly to disable the

Software Data Protection the user has to write

specific data bytes into six different locations as per

Figure 6 (with a Page Write). This complex series

ensures that the user will never enable or disable

the Software Data Protection accidentally.

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