MT46V16M16 データシートの表示（PDF） - Micron Technology
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MT46V16M16 Datasheet PDF : 8 Pages
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PRELIMINARY
256Mb: x4, x8, x16
DDR333 SDRAM Addendum
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 1-5, 14-17, 33; notes appear in DDR200/266 data sheets)
(0°C ≤ TA ≤ 70°C; VDDQ = +2.5V ±0.2V, VDD = +2.5V ±0.2V)
AC CHARACTERISTICS
-6 (FBGA)
-6T (TSOP)
-75Z
PARAMETER
SYMBOL
Access window of DQs from CK/CK#
tAC
CK high-level width
tCH
CK low-level width
tCL
Clock cycle time
CL = 2.5 tCK (2.5)
CL = 2
tCK (2)
DQ and DM input hold time relative to DQS
tDH
DQ and DM input setup time relative to DQS
tDS
DQ and DM input pulse width (for each input)
tDIPW
Access window of DQS from CK/CK#
tDQSCK
DQS input high pulse width
tDQSH
DQS input low pulse width
tDQSL
DQS-DQ skew, DQS to last DQ valid, per group, per access tDQSQ
Write command to first DQS latching transition
tDQSS
DQS falling edge to CK rising - setup time
tDSS
DQS falling edge from CK rising - hold time
tDSH
Half clock period
tHP
Data-out high-impedance window from CK/CK#
tHZ
Data-out low-impedance window from CK/CK#
tLZ
Address and control input hold time (fast slew rate)
Address and control input setup time (fast slew rate)
Address and control input hold time (slow slew rate)
Address and control input setup time (slow slew rate)
Address and control input pulse width
tIHF
tIS
F
tIH
S
tIS
S
tIPW
LOAD MODE REGISTER command cycle time
tMRD
DQ-DQS hold, DQS to first DQ to go non-valid, per access tQH
Data Hold Skew Factor
ACTIVE to AUTOPRECHARGE command
ACTIVE to PRECHARGE command
ACTIVE to ACTIVE/AUTO REFRESH command period
AUTO REFRESH command period
ACTIVE to READ or WRITE delay
PRECHARGE command period
DQS read preamble
DQS read postamble
ACTIVE bank a to ACTIVE bank b command
DQS write preamble
DQS write preamble setup time
DQS write postamble
Write recovery time
Internal WRITE to READ command delay
Data valid output window
REFRESH to REFRESH command interval
Average periodic refresh interval
Terminating voltage delay to VDD
Exit SELF REFRESH to non-READ command
Exit SELF REFRESH to READ command
tQHS
tRAP
tRAS
tRC
tRFC
tRCD
tRP
tRPRE
tRPST
tRRD
tWPRE
tWPRES
tWPST
tWR
tWTR
na
tREFC
tREFI
tVTD
tXSNR
tXSRD
MIN MAX
-0.7 +0.7
0.45 0.55
0.45 0.55
6
13
7.5
13
0.45
0.45
1.75
-0.60 +0.60
0.35
0.35
0.35
0.75 1.25
0.2
0.2
tCH,tCL
+0.70
-0.70
0.75
0.75
0.80
0.80
2.2
12
tHP
- tQHS
0.50
18
42 70,000
60
72
18
18
0.9 1.1
0.4 0.6
12
0.25
0
0.4 0.6
15
1
tQH - tDQSQ
70.3
7.8
0
75
200
MIN MAX
-0.7 +0.7
0.45 0.55
0.45 0.55
6
13
7.5
13
0.45
0.45
1.75
-0.60 +0.60
0.35
0.35
0.45
0.75 1.25
0.2
0.2
tCH,tCL
+0.70
-0.70
0.75
0.75
0.80
0.80
2.2
12
tHP
- tQHS
0.60
18
42 70,000
60
72
18
18
0.9 1.1
0.4 0.6
12
0.25
0
0.4 0.6
15
1
tQH - tDQSQ
70.3
7.8
0
75
200
MIN MAX UNITS NOTES
-0.75 +0.75 ns
0.45 0.55 tCK 30
0.45 0.55 tCK 30
7.5
13
ns 45,52
7.5
13
ns 45,52
0.50
ns 26,31
0.50
ns 26,31
1.75
ns 31
-0.75 +0.75 ns
0.35
tCK
0.35
tCK
0.50
0.75 1.25
0.2
0.2
tCH,tCL
ns 25, 26
tCK
tCK
tCK
ns 34
+0.75 ns 18,42
-0.75
ns 18,43
0.90
ns 14
0.90
ns 14
1
ns 14
1
ns 14
2.2
ns
15
tHP
- tQHS
ns
ns 25, 26
0.75 ns
20
ns 46
40 120,000 ns 35
65
ns
75
ns 50
20
ns
20
ns
0.9
1.1 tCK 42
0.4
0.6 tCK
15
ns
0.25
tCK
0
ns 20, 21
0.4
0.6 tCK 19
15
ns
1
tCK
tQH - tDQSQ
ns
25
70.3 µs 23
7.8 µs 23
0
ns
75
ns
200
tCK
256Mb: x4, x8, x16 DDR333 SDRAM
256Mx4x8x16DDR333_B.p65 – Rev. B; Pub. 10/01
7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
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