MT48LC2M32B2 データシートの表示（PDF） - Micron Technology

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MT48LC2M32B2

SYNCHRONOUS DRAM

Micron Technology 

Commands

Truth Table 1 provides a quick reference of avail-

able commands. This is followed by a written descrip-

tion of each command. Three additional Truth Tables

64Mb: x32

SDRAM

appear following the Operation section; these tables

provide current state/next state information.

TRUTH TABLE 1 – COMMANDS AND DQM OPERATION

(Note: 1)

NAME (FUNCTION)

COMMAND INHIBIT (NOP)

NO OPERATION (NOP)

ACTIVE (Select bank and activate row)

READ (Select bank and column, and start READ burst)

WRITE (Select bank and column, and start WRITE burst)

BURST TERMINATE

PRECHARGE (Deactivate row in bank or banks)

AUTO REFRESH or SELF REFRESH

(Enter self refresh mode)

LOAD MODE REGISTER

Write Enable/Output Enable

Write Inhibit/Output High-Z

CS# RAS# CAS# WE# DQM ADDR DQs NOTES

HXXXX

X

X

L HHHX

X

X

L L H H X Bank/Row X

3

L H L H L/H8 Bank/Col X

4

L

H

L

L L/H8 Bank/Col Valid 4

LHHL X

X

Active

L LHLX

Code

X

5

L L LHX

X

X

6, 7

L L L L X Op-Code X

2

––––L

–

Active 8

– – – –H

–

High-Z 8

NOTE:

1. CKE is HIGH for all commands shown except SELF REFRESH.

2. A0-A10 define the op-code written to the Mode Register.

3. A0-A10 provide row address, BA0 and BA1 determine which bank is made active.

4. A0-A7 provide column address; A10 HIGH enables the auto precharge feature (nonpersistent), while

A10 LOW disables the auto precharge feature; BA0 and BA1 determine which bank is being read from

or written to.

5. A10 LOW: BA0 and BA1 determine the bank being precharged. A10 HIGH: All banks precharged and

BA0 and BA1 are “Don’t Care.”

6. This command is AUTO REFRESH if CKE is HIGH; SELF REFRESH if CKE is LOW.

7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.

8. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay). DQM0

controls DQ0-DQ7; DQM1 controls DQ8-DQ15; DQM2 controls DQ16-DQ23; and DQM3 controls

DQ24-DQ31.

64Mb: x32 SDRAM

64MSDRAMx32_5.p65 – Rev. B; Pub. 6/02

9

Micron Technology, Inc., reserves the right to change products or specifications without notice.

©2002, Micron Technology, Inc.

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