MT48LC16M8A2TG-7ELIT データシートの表示（PDF） - Micron Technology

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MT48LC16M8A2TG-7ELIT

SYNCHRONOUS DRAM

Micron Technology 

This is shown in Figure 7 for CAS latencies of two and

three; data element n + 3 is either the last of a burst of four

or the last desired of a longer burst. The 128Mb SDRAM

uses a pipelined architecture and therefore does not

require the 2n rule associated with a prefetch architec-

128Mb: x4, x8, x16

SDRAM

ture. A READ command can be initiated on any clock

cycle following a previous READ command. Full-speed

random read accesses can be performed to the same

bank, as shown in Figure 8, or each subsequent READ

may be performed to a different bank.

T0

T1

T2

T3

T4

T5

T6

CLK

COMMAND

READ

NOP

NOP

NOP

READ

NOP

NOP

ADDRESS

BANK,

COL n

X = 1 cycle

BANK,

COL b

DQ

CAS Latency = 2

DOUT

n

DOUT

n+1

DOUT

n+2

DOUT

n+3

DOUT

b

T0

T1

T2

T3

T4

T5

T6

T7

CLK

COMMAND

READ

NOP

NOP

NOP

READ

NOP

NOP

NOP

ADDRESS

BANK,

COL n

BANK,

COL b

X = 2 cycles

DQ

DOUT

n

DOUT

n+1

DOUT

n+2

CAS Latency = 3

NOTE: Each READ command may be to any bank. DQM is LOW.

Figure 7

Consecutive READ Bursts

DOUT

n+3

DOUT

b

DON’T CARE

128Mb: x4, x8, x16 SDRAM

128MSDRAM_E.p65 – Rev. E; Pub. 1/02

17

Micron Technology, Inc., reserves the right to change products or specifications without notice.

©2001, Micron Technology, Inc.

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