MT48LC16M8A2TG-7ELIT データシートの表示（PDF） - Micron Technology
部品番号
コンポーネント説明
メーカー
MT48LC16M8A2TG-7ELIT Datasheet PDF : 59 Pages
| |||
A fixed-length READ burst may be followed by, or
truncated with, a PRECHARGE command to the same
bank (provided that auto precharge was not activated),
and a full-page burst may be truncated with a
PRECHARGE command to the same bank. The
PRECHARGE command should be issued x cycles before
the clock edge at which the last desired data element is
valid, where x equals the CAS latency minus one. This is
shown in Figure 11 for each possible CAS latency; data
element n + 3 is either the last of a burst of four or the last
128Mb: x4, x8, x16
SDRAM
desired of a longer burst. Following the PRECHARGE
command, a subsequent command to the same bank
cannot be issued until tRP is met. Note that part of the row
precharge time is hidden during the access of the last
data element(s).
In the case of a fixed-length burst being executed to
completion, a PRECHARGE command issued at the opti-
mum time (as described above) provides the same op-
eration that would result from the same fixed-length
burst with auto precharge. The disadvantage of the
T0
T1
CLK
COMMAND
READ
NOP
ADDRESS
BANK a,
COL n
T2
NOP
T3
T4
T5
T6
t RP
NOP
PRECHARGE
NOP
NOP
X = 1 cycle
BANK
(a or all)
T7
ACTIVE
BANK a,
ROW
DQ
DOUT
n
DOUT
n+1
DOUT
n+2
DOUT
n+3
CAS Latency = 2
T0
T1
CLK
COMMAND
READ
NOP
ADDRESS
BANK a,
COL n
T2
NOP
T3
T4
T5
T6
t RP
NOP
PRECHARGE
NOP
NOP
BANK
(a or all)
X = 2 cycles
T7
ACTIVE
BANK a,
ROW
DQ
DOUT
n
DOUT
n+1
DOUT
n+2
CAS Latency = 3
NOTE: DQM is LOW.
Figure 11
READ to PRECHARGE
DOUT
n+3
DON’T CARE
128Mb: x4, x8, x16 SDRAM
128MSDRAM_E.p65 – Rev. E; Pub. 1/02
20
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
Share Link: 