MT54W1MH36BF-4 データシートの表示（PDF） - Micron Technology

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MT54W1MH36BF-4

36Mb QDR™II SRAM 2-WORD BURST

Micron Technology 

ADVANCE

4 MEG x 8, 4 MEG x 9, 2 MEG x 18, 1 MEG x 36

1.8V VDD, HSTL, QDRIIb2 SRAM

CLOCK CONSIDERATIONS

This device utilizes internal delay-locked loops for

maximum output data valid window. It can be placed

into a stopped-clock state to minimize power with a

modest restart time of 1,024 clock cycles. Circuitry

automatically resets the DLL when the absence of

input clock is detected. See Micron Technical Note TN-

54-02 for more information on clock DLL start-up pro-

cedures.

SINGLE CLOCK MODE

The SRAM can be used with the single K, K# clock

pair by tying C and C# HIGH. In this mode, the SRAM

will use K and K# in place of C and C#. This mode pro-

vides the most rapid data output but does not com-

pensate for system clock skew and flight times.

DEPTH EXPANSION

Port select inputs are provided for the read and

write ports. This allows for easy depth expansion. Both

port selects are sampled on the rising edge of K only.

Each port can be independently selected and dese-

lected and does not affect the operation of the oppo-

site port. All pending transactions are completed prior

to a port deselecting. Depth expansion requires repli-

cating R# and W# control signals for each bank if it is

desired to have the bank independent of READ and

WRITE operations.

36Mb: 1.8V VDD, HSTL, QDRIIb2 SRAM

MT54W2MH18B_A.fm - Rev 9/02

4

Micron Technology, Inc., reserves the right to change products or specifications without notice.

©2002, Micron Technology Inc.

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