MT8888 データシートの表示（PDF） - Mitel Networks

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MT8888

Integrated DTMF Transceiver with Intel Micro Interface

Mitel Networks 

MT8888C/MT8888C-1

The Fourier components of the tone output

correspond to V2f.... Vnf as measured on the output

waveform. The total harmonic distortion for a dual

tone can be calculated using Equation 2. VL and VH

correspond to the low group amplitude and high

group amplitude, respectively and V2IMD is the sum

of all the intermodulation components. The internal

switched-capacitor filter following the D/A converter

keeps distortion products down to a very low level as

shown in Figure 10.

V22L + V23L + .... V2nL + V22H +

V23H + .. V2nH + V2IMD

THD (%) = 100

V2L + V2H

Equation 2. THD (%) For a Dual Tone

DTMF Clock Circuit

The internal clock circuit is completed with the

addition of a standard television colour burst crystal.

The crystal specification is as follows:

Frequency:

3.579545 MHz

Frequency Tolerance:

±0.1%

Resonance Mode:

Parallel

Load Capacitance:

18pF

Maximum Series Resistance:150 ohms

Maximum Drive Level:

2mW

e.g. CTS Knights MP036S

Toyocom TQC-203-A-9S

A number of MT8888C/MT8888C-1 devices can be

connected as shown in Figure 11 such that only one

crystal is required. Alternatively, the OSC1 inputs on

all devices can be driven from a TTL buffer with the

OSC2 outputs left unconnected.

MT8888C/

MT8888C-1

OSC1 OSC2

MT8888C/

MT8888C-1

OSC1 OSC2

MT8888C/

MT8888C-1

OSC1 OSC2

3.579545 MHz

Figure 11 - Common Crystal Connection

Microprocessor Interface

The MT8888C/MT8888C-1 incorporates an Intel

microprocessor interface which is compatible with

fast versions (16 MHz) of the 80C51. No wait cycles

need to be inserted.

4-98

Figures 17 and 18 are the timing diagrams for the

Intel 8031, 8051 and 8085 (5 MHz) microcontrollers.

By NANDing the address latch enable (ALE) output

with the high-byte address (P2) decode output, CS is

generated. Figure 12 summarizes the connection of

these Intel processors to the MT8888C/MT8888C-1

transceiver.

The microprocessor interface provides access to five

internal registers. The read-only Receive Data

Register contains the decoded output of the last

valid DTMF digit received. Data entered into the

write-only Transmit Data Register will determine

which tone pair is to be generated (see Table 1 for

coding details). Transceiver control is accomplished

with two control registers (see Tables 6 and 7), CRA

and CRB, which have the same address. A write

operation to CRB is executed by first setting the

most significant bit (b3) in CRA. The following write

operation to the same address will then be directed

to CRB, and subsequent write cycles will be directed

back to CRA. The read-only status register indicates

the current transceiver state (see Table 8).

A software reset must be included at the beginning

of all programs to initialize the control registers upon

power-up or power reset (see Figure 17). Refer to

Tables 4-7 for bit descriptions of the two control

registers.

The multiplexed IRQ/CP pin can be programmed to

generate an interrupt upon validation of DTMF

signals or when the transmitter is ready for more

data (burst mode only). Alternatively, this pin can be

configured to provide a squarewave output of the call

progress signal. The IRQ/CP pin is an open drain

output and requires an external pull-up resistor (see

Figure 13).

RS0

WR

RD

FUNCTION

0

0

1

Write to Transmit

Data Register

0

1

0

Read from Receive

Data Register

1

0

1

Write to Control Register

1

1

0

Read from Status Register

Table 3. Internal Register Functions

b3

RSEL

b2

b1

b0

IRQ

CP/DTMF

TOUT

Table 4. CRA Bit Positions

b3

b2

b1

b0

C/R

S/D

TEST

BURST

ENABLE

Table 5. CRB Bit Positions

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