MT8889CN データシートの表示（PDF） - Mitel Networks

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MT8889CN

Integrated DTMFTransceiver with Adaptive Micro Interface

Mitel Networks 

MT8889C/MT8889C-1

The Fourier components of the tone output

correspond to V2f.... Vnf as measured on the output

waveform. The total harmonic distortion for a dual

tone can be calculated using Equation 2. VL and VH

correspond to the low group amplitude and high

group amplitude, respectively and V2IMD is the sum

of all the intermodulation components. The internal

switched-capacitor filter following the D/A converter

keeps distortion products down to a very low level as

shown in Figure 10.

V22L + V23L + .... V2nL + V22H +

V23H + .. V2nH + V2IMD

THD (%) = 100

V2L + V2H

Equation 2. THD (%) For a Dual Tone

DTMF Clock Circuit

The internal clock circuit is completed with the

addition of a standard television colour burst

crystal. The crystal specification is as follows:

Frequency:

3.579545 MHz

Frequency Tolerance:

±0.1%

Resonance Mode:

Parallel

Load Capacitance:

18pF

Maximum Series Resistance:150 ohms

Maximum Drive Level:

2mW

e.g. CTS Knights MP036S

Toyocom TQC-203-A-9S

A number of MT8889C/MT8889C-1 devices can be

connected as shown in Figure 11 such that only one

crystal is required. Alternatively, the OSC1 inputs on

all devices can be driven from a TTL buffer with the

OSC2 outputs left unconnected.

MT8889C/

MT8889C-1

OSC1 OSC2

MT8889C/

MT8889C-1

OSC1 OSC2

MT8889C/

MT8889C-1

OSC1 OSC2

3.579545 MHz

Figure 11 - Common Crystal Connection

Microprocessor Interface

The MT8889C/MT8889C-1 design incorporates an

adaptive interface, which allows it to be connected to

4-114

various kinds of microprocessors. Key functions of

this interface include the following:

• Continuous activity on DS/RD is not necessary

to update the internal status registers.

• senses whether input timing is that of an Intel or

Motorola controller by monitoring the DS (RD),

R/W (WR) and CS inputs.

• generates equivalent CS signal for internal

operation for all processors.

• differentiates between multiplexed and non-

multiplexed microprocessor buses. Address

and data are latched in accordingly.

• compatible with Motorola and Intel processors.

Figure 17 shows the timing diagram for Motorola

microprocessors with separate address and data

buses. Members of this microprocessor family

include 2 MHz versions of the MC6800, MC6802 and

MC6809. For the MC6809, the chip select (CS) input

signal is formed by NANDing the (E+Q) clocks and

address decode output. For the MC6800 and

MC6802, CS is formed by NANDing VMA and

address decode output. On the falling edge of CS,

the internal logic senses the state of data strobe

(DS). When DS is low, Motorola processor operation

is selected.

Figure 18 shows the timing diagram for the Motorola

MC68HC11 (1 MHz) microcontroller. The chip select

(CS) input is formed by NANDing address strobe

(AS) and address decode output. Again, the

MT8889C/MT8889C-1 examines the state of DS on

the falling edge of CS to determine if the micro has a

Motorola bus (when DS is low). Additionally, the

Texas Instruments TMS370CX5X is qualified to have

a Motorola interface. Figure 12(a) summarizes

connection of these Motorola processors to the

MT8889C/MT8889C-1 DTMF transceiver.

Figures 19 and 20 are the timing diagrams for the

Intel 8031/8051 (12 MHz) and 8085 (5 MHz) micro-

controllers with multiplexed address and data buses.

The MT8889C/MT8889C-1 latches in the state of RD

on the falling edge of CS. When RD is high, Intel

processor operation is selected. By NANDing the

address latch enable (ALE) output with the high-byte

address (P2) decode output, CS can be generated.

Figure 12(b) summarizes the connection of these

Intel processors to the MT8889C/MT8889C-1

transceiver.

NOTE: The adaptive micro interface relies on high-

to-low transition on CS to recognize the

microcontroller interface and this pin must not be tied

permanently low.

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