MT8930CC データシートの表示（PDF） - Mitel Networks
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MT8930CC Datasheet PDF : 36 Pages
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MT8930C
Preliminary Information
HALF 1
C4b 2
F0b 3
F0od 4
DSTi 5
DSTo 6
Cmode 7
CK/NT 8
R/W/WR, AFT/PRI 9
DS/RD, DinB 10
AS/ALE, P/SC 11
CS, DReq 12
IRQ/NDA, DCack 13
VSS 14
28 VDD
27 VBias
26 LTx
25 LRx
24 STAR/Rsto
F0od
DSTi
23 Rsti
DSTo
22 AD7, DR
NC
21 AD6, AR
NC
20 AD5, M/S
NC
19 AD4, MCH
Cmode
18
17
16
15
AD3, MFR
AD2, SYNC/BA
AD1, IS1
AD0, IS0
CK/NT
NC
R/W/WR, AFT/PRI
DS/RD, DinB
6 5 4 3 2 1 44 43 42 41 40
7
39
8
38
9
37
10
36
11
35
12
34
13
33
14
32
15
31
16
30
17
29
18 19 20 21 22 23 24 25 26 27 28
NC
STAR/Rsto
Rsti
NC
AD7, DR
AD6, AR
NC
AD5, M/S
AD4, MCH
AD3, MFR
NC
28 PIN PDIP/CERDIP
44 PIN PLCC
Pin Description
Pin #
DIP PLCC
Name
12
HALF
23
34
47
C4b
F0b
F0od
58
DSTi
69
DSTo
7 13 Cmode
8 14
CK/NT
Figure 2 - Pin Connections
Description
HALF Input/Output: this is an input in NT mode and an output in TE mode identifying
which half of the S-interface frame is currently being written/read over the ST-BUS
(HALF = 0 sampled on the falling edge of C4b within the frame pulse low window,
identifies the information to be transmitted/received in the first half of the S-Bus frame
while HALF = 1 identifies the information to be transmitted/received into the second half
of the S-Bus frame). Tying this pin to VSS or VDD in NT mode will allow the device to
free run. This signal can also be accessed from the ST-BUS C-channel.
4.096 MHz Clock: a 4.096 MHz ST-BUS Data Clock input in NT mode.
In TE mode, a 4.096 MHz output clock phase-locked to the line data signal.
Frame Pulse: an active low frame pulse input indicating the beginning of active ST-
BUS channel times in NT mode. Frame pulse output in TE mode.
Delayed Frame Pulse Output: an active low delayed frame pulse output indicating
the end of active ST-BUS channels for this device. Can be used to daisy chain
to other ST-BUS devices to share an ST-BUS stream.
Data ST-BUS Input: a 2048 kbit/s serial PCM/data ST-BUS input with D, C, B1, and B2
channels assigned to the first four timeslots. These channels contain data to be
transmitted on the line and chip control information.
Data ST-BUS Output: a 2048 kbit/s serial PCM/data ST-BUS output with D, C, B1 and
B2 channels assigned to the first four timeslots respectively. The remaining timeslots
are placed into high impedance. These channels contain data received from the line
and chip status information.
Controller Mode Select Input: when high, microprocessor control is selected. When
low the controllerless mode is enabled and the microport pins are redefined as control
inputs and status outputs.
TE Clock/Network Termination Mode Select Input. For TE mode, this pin must be
tied to VSS or to a 4.096 MHz clock (a clock is required for standard ISDN TE
applications). For NT mode, this pin must be tied to VDD. Refer to “ST-BUS Interface”
section for further explanation. A pull-up resistor is needed when driven by a TTL
device.
9-36
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