MT8930CC データシートの表示（PDF） - Mitel Networks
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MT8930CC Datasheet PDF : 36 Pages
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Preliminary Information
MT8930C
Functional Description
The MT8930C Subscriber Network Interface Circuit
(SNIC) is a multifunction transceiver providing a
complete interface to the S/T Reference Point as
specified in ETS 300-012, CCITT Recommendation
I.430 and ANSI T1.605. Implementing both
point-to-point and point-to-multipoint voice/data
transmission, the SNIC may be used at either end of
the digital subscriber loop. A programmable digital
interface allows the MT8930C to be configured as a
Network Termination (NT) or as a Terminal
Equipment (TE) device.
The SNIC supports 192 kbit/s (2B+D + overhead) full
duplex data transmission on a 4-wire balanced
transmission line. Transmission capability for both B
and D channels, as well as related timing and
synchronization functions, are provided on chip. The
signalling capability and procedures necessary to
enable customer terminals (TEs) to be activated and
deactivated, form part of the MT8930C’s
functionality. The SNIC handles D-channel resource
allocation and prioritization for access contention
resolution and signalling requirements in passive bus
line configurations. Control and status information
allows implementation of maintenance functions and
monitoring of the device and the subscriber loop.
An HDLC transceiver is included on the SNIC for link
access protocol handling via the D-channel.
Depacketized data is passed to and from the
transceiver via the microprocessor port. Two 19 byte
deep FIFOs, one for transmit and one for receive,
are provided to buffer the data. The HDLC block can
be set up to transmit or receive to/from either the
S-interface port or the ST-BUS port. Further, the
transmit destination and receive source can be
independently selected, e.g., transmit to S-interface
while receiving from ST-BUS. The transmit and
receive paths can be separately enabled or disabled.
Both, one and two byte address recognition is
supported by the SNIC. A transparent mode allows
data to be passed directly to the D channel without
being packetized.
A block diagram of the MT8930C is shown in Figure
1. The SNIC has three interface ports: a 4-wire
CCITT compatible S/T interface (subscriber loop
interface), a 2048 kbit/s ST-BUS serial port, and a
general purpose parallel microprocessor port. This
8-bit parallel port is compatible with both Motorola or
HALF
C4bi
F0bi
F0od
DSTi
DSTo
Cmode
NT
R/W/WR
DS/RD
AS/ALE
CS
IRQ, NDA
VSS
NT MODE
1
28
2
27
3
26
4
25
5
24
6
23
7
22
8
21
9
20
10
19
11
18
12
17
13
16
14
15
CONTROLLER MODE
VDD
VBias
LTx
LRx
STAR
Rsti
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
HALF
C4bo
F0bo
F0od
DSTi
DSTo
Cmode
CK
R/W/WR
DS/RD
AS/ALE
CS
IRQ, NDA
VSS
TE MODE
1
28
2
27
3
26
4
25
5
24
6
23
7
22
8
21
9
20
10
19
11
18
12
17
13
16
14
15
VDD
VBias
LTx
LRx
Rsto
Rsti
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
NT MODE
CONTROLLERLESS MODE
TE MODE
HALF 1
C4bi 2
F0bi 3
F0od 4
DSTi 5
DSTo 6
Cmode 7
NT 8
AFT 9
DinB 10
P/SC 11
IC 12
IC 13
VSS 14
28 VDD
27 VBias
26 LTx
25 LRx
24 STAR
23 Rsti
22 DR
21 AR
20 M/Si
19 MCHo
18 MFRi
17 SYNC/BA
16 IS1
15 IS0
HALF 1
C4bo 2
F0bo 3
F0od 4
DSTi 5
DSTo 6
Cmode 7
CK 8
PRI 9
DinB 10
P/SC 11
DReq 12
DCack 13
VSS 14
28 VDD
27 VBias
26 LTx
25 LRx
24 Rsto
23 Rsti
22 DR
21 AR
20 M/So
19 MCHi
18 MFRo
17 SYNC/BA
16 IS1
15 IS0
Figure 3 - SNIC Pin Connections in Various Modes
9-39
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