PDM31532SA10TI データシートの表示（PDF） - Paradigm Technology

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PDM31532SA10TI

64K x 16 CMOS 3.3V Static RAM

Paradigm Technology 

Features

n High-speed access times

- Com’l: 9, 10, 12, 15 and 20 ns

- Ind: 12, 15 and 20 ns

n Low power operation (typical)

- PDM31532LA

Active: 200 mW

Standby: 10 mW

- PDM31532SA

Active: 250 mW

Standby: 20 mW

n High-density 64K x 16 architecture

n 3.3V (±0.3V) power supply

n Fully static operation

n TTL-compatible inputs and outputs

n Output buffer controls: OE

n Data byte controls: LB, UB

n Packages:

Plastic SOJ (400 mil) - SO

Plastic TSOP - T (II)

Functional Block Diagram

A8-A0

I/O15-I/O0

Data

Input/

Output

Buffer

WE

OE

UB Control

LB

Logic

CE

Rev. 4.3 - 3/27/98

PDMPD3M135135322

64K x 16 CMOS

3.3V Static RAM

1

Description

2 The PDM31532 is a high-performance CMOS static

RAM organized as 65,536 x 16 bits. The PDM31532

features low power dissipation using chip enable

(CE) and has an output enable input (OE) for fast

3 memory access. Byte access is supported by upper

and lower byte controls.

The PDM31532 operates from a single 3.3V power

supply and all inputs and outputs are fully TTL-

compatible.

4

The PDM31532 is available in a 44-pin 400 mil plas-

tic SOJ and a plastic TSOP (II) package for high-

5 density surface assembly and is suitable for use in

high-speed applications requiring high-speed

storage.

6

7

Memory

Vcc

Vss

8

Cell

Array

25632xK12x83x2 32

9

Clock

Generator

Sense Amp

Column

Decoder

Column

Address

Buffer

A15-A9

10

11

12

1

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