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MT9080B データシートの表示(PDF) - Mitel Networks

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MT9080B
Mitel
Mitel Networks Mitel
MT9080B Datasheet PDF : 25 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
MT9080B CMOS
D8i
12
D9i
D10i
14
D11i
VSS
16
D12i
D13i
18
D14i
D15i
20
VSS
CK
22
VDD
VSS
24
IC
IC
26
FP
CS
28
DS
R/W
30
DTA
NC
32
84 PIN PLCC
74
VSS
D7o
72
D6o
D5o
70
D4o
VSS
68
D3o
D2o
66
D1o
D0o
64
VSS
VDD
62
CD
A15
60
A14
A13
58
A12
A11
56
A10
A9
54
A8
Figure 2 - Pin Connections
Pin Description
Pin # Name
Description
1
VSS Ground.
2-5 D0i-D3i Input/Microport Data Bus. This is part of a 16 bit data bus. The data bus is bidirectional in
Connect Memory mode where it is typically interfaced to a microprocessor. In all other
modes the data bus is an input. Data to be switched through the device is clocked in at this
port.
6
7-10
VSS Ground.
D4i-D7i Input/Microport Data Bus. See description for pins 2-5 above.
11
VSS Ground.
12-15 D8i-D11i Input/Microport Data Bus. See description for pins 2-5 above.
16
VSS Ground.
17-20 D12i-D15i Input/Microport Data Bus. See description for pins 2-5 above.
21
VSS Ground.
22
CK Clock. Master clock input which is used to clock data into and out of the device. It also clocks
the internal 11 bit counter.
23
24
25,26
27
VDD +5V supply input.
VSS Ground.
IC Internal Connection. Should be tied to VSS for normal operation.
FP Frame Pulse. An active low signal that serves as a synchronous clear for the internal 11 bit
counter in all modes except Shift Register mode. The counter is cleared on a rising edge of
CK. In the Shift Register mode, FP serves to align channel boundaries.
2-102

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