MT90812AL データシートの表示（PDF） - Mitel Networks

部品番号

コンポーネント説明

メーカー

MT90812AL

Integrated Digital Switch (IDX)

Mitel Networks 

MT90812

Advance Information

Pin Description

Pin #

64 Pin 68 Pin

MQFP PLCC

Name

Description

1

2-11

25-26

27-36

NC

A0 - A9

No Connect. Ground

Address 0 - 9(Input). When non-multiplexed CPU bus is selected, these lines

provide the A0 - A9 address lines to IDX internal memories.

12

37

DS/RD Data Strobe/Read (Input). For Motorola multiplexed bus operation, this active

high DS input works with CS to enable the read and write operations.

For Motorola non-multiplexed CPU bus operation, this input is DS. This active low

input works in conjunction with CS to enable the read and write operations.

For Intel/National multiplexed bus operations, this input is RD. This active low

input sets the data bus lines (AD0-AD7) as outputs.

13

38 R/W \ WR Read/Write \ Write (Input). In case of non-multiplexed and Motorola multiplexed

buses, this input is Read/Write. This input controls the direction of the data bus

lines (AD0 - AD7) during a microprocessor access.

For Intel/National multiplexed bus, this input is WR. This active low signal

configures the data bus lines (AD0-AD7) as inputs.

14

39

CS Chip Select (Input). Active low input enabling a microprocessor read or write of

internal memories.

15

40 AS/ALE Address Strobe or Latch Enable (Input). This input is only used if multiplexed

bus is selected via IM input pin.

16

41

IM CPU Interface Mode (Input). If High, this input sets the device in the multiplexed

microprocessor mode. If this input is grounded, the device resumes non-

multiplexed CPU interface.

17

42

DTA Data Acknowledgment (Open Drain Output). This active low output indicates

that a data bus transfer is complete. A 10Kohm pull-up resistor is required at this

output.

18

43

IRQ Interrupt Request Output (Open Drain Output). This active low output notifies

the controlling microprocessor of an interrupt request. It goes Low only when the

bits in the Interrupt Enable Register are programmed to acknowledge the source

of the interrupt as defined in the Interrupt Status Register.

-

44

NC No Connect. Ground

19

45

VSS5 Ground.

20-27

46-53 AD0 - AD7 Data Bus (Bidirectional). These pins provide microprocessor access to the

internal memories. In the multiplexed bus mode, these pins also provide the input

address to the internal Address Latch circuit.

28

54

VSS1 Ground.

29

55

TEOP Transmit End of Packet (Input). This is a strobe that is generated by the HDLC

controller chip for one bit period during the last bit of the closing flag of the

transmit packet.

30

56

REOP Receive End of Packet (Input). A receive packet will normally be terminated

when the HDLC controller asserts the REOP strobe for one bit period, one bit time

after the closing flag is received.

31

57

TxCEN Transmit Clock Enable (Output). The HDLC transmitter is controlled by the IDX-

generated Transmit Clock Enable signal, TxCEN.

32

58

RxCEN Receive Clock Enable (Output). The HDLC receiver is controlled by the IDX-

generated Receive Clock Enable signal, RxCEN.

4

Share Link: