LTC1663C データシートの表示（PDF） - Linear Technology

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LTC1663C

10-Bit Rail-to-Rail Micropower DAC with 2-Wire Interface

Linear Technology 

LTC1663

DEFINITIONS

Integral Nonlinearity (INL): The deviation from a straight

line passing through the endpoints of the DAC transfer

curve (Endpoint INL). Because the output cannot go

below zero, the linearity is measured between full scale

and the lowest code that guarantees the output will be

greater than zero. The INL error at a given input code is

calculated as follows:

INL = [VOUT – VOS – (VFS – VOS)(code/1023)]/LSB

Where VOUT is the output voltage of the DAC measured

at the given input code.

Least Significant Bit (LSB): The ideal voltage difference

between two successive codes.

LSB = VREF/1024

Resolution (n): Defines the number of DAC output states

(2n) that divide the full-scale range. Resolution does not

imply linearity.

Voltage Offset Error (VOS): Nominally, the voltage at the

output when the DAC is loaded with all zeros. A single

supply DAC can have a true negative offset, but the output

cannot go below zero (see Applications Information).

For this reason, single supply DAC offset is measured at

the lowest code that guarantees the output will be greater

than zero.

APPLICATIONS INFORMATION

Write Word Protocol Used by the LTC1663

1

7

11

8

1

8

1

S Slave Address Wr A Command Byte A LSData Byte A

S = Start Condition, Wr = Write Bit = 0, A = Acknowledge, P = Stop Condition

8

MSData Byte

11

AP

1663 TA03

Serial Digital Interface

The LTC1663 communicates with a host (master) using

the standard 2-wire interface. The Timing Diagram shows

the timing relationship of the signals on the bus. The two

bus lines, SDA and SCL, must be high when the bus is

not in use. External pull-up resistors or current sources,

such as the LTC1694 SMBus Accelerator, are required on

these lines.

The LTC1663 is a receive-only (slave) device. The master

can communicate with the LTC1663 using the Quick Com-

mand, Send Byte or Write Word protocols as explained

later.

The START and STOP Conditions

When the bus is not in use, both SCL and SDA must be

high. A bus master signals the beginning of a communica-

tion to a slave device by transmitting a START condition.

A START condition is generated by transitioning SDA

from high to low while SCL is high.

When the master has finished communicating with the

slave, it issues a STOP condition. A STOP condition is

generated by transitioning SDA from low to high while

SCL is high. The bus is then free for communication with

another SMBus device.

Acknowledge

The Acknowledge signal is used for handshaking between

the master and the slave. An Acknowledge (active LOW)

generated by the slave lets the master know that the latest

byte of information was received. The Acknowledge related

clock pulse is generated by the master. The master releases

the SDA line (HIGH) during the Acknowledge clock pulse.

The slave-receiver must pull down the SDA line during the

Acknowledge clock pulse so that it remains a stable LOW

during the HIGH period of this clock pulse.

Write Word Protocol

The master initiates communication with the LTC1663 with

a START condition and a 7-bit address followed by the Write

1663fd

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