MT90881 データシートの表示（PDF） - Zarlink Semiconductor Inc

部品番号

コンポーネント説明

メーカー

MT90881

TDM to Packet Processors

Zarlink Semiconductor Inc 

MT90880/1/2/3

Data Sheet

The following external documents and standards are referenced in this data sheet:

Title

Author

Document

Number

1. Local and Metropolitan Area Networks, Part 3: Carrier

sense multiple access with collision detection

(CSMA/CD) access method and physical layer specifi-

cations

2. PCI Local Bus Specification

3. RMII TM Specification

4. Test Access Port and Boundary Scan Architecture

5. Circuit Emulation Service Interoperability Specification

6. Specifications of (DBCES) Dynamic Bandwidth Utiliza-

tion - in 64 KBPS Time Slot Trunking over ATM - Using

CES

7. ST-BUS Generic Device Specification

8. H.110 Hardware Compatibility Specification: CT Bus

9. H-MVIP Standard

10. Clocks for the Synchronized Network: Common Generic Cri-

teria

11. The Control of Jitter and Wander within digital networks

which are based on the 2048 Kbs hierarchy

12. The Control of Jitter and Wander within digital networks

which are based on the 1544 Kbs hierarchy

IEEE

IEEE 802.3u

PCI SIG

RMII

consortium

IEEE

ATM Forum

ATM Forum

IEEE 1149.1

af-vtoa-0078

af-vtoa-0085

Mitel

ECTF

GO-MVIP

Telcordia

ITU-T

MSAN-126

GR-1244-

CORE

G.823

ITU-T

G.824

Table 3 - Referenced Documents

Issue / Date

1995

2.2

Rev 1.2, March 1998

1990

Ver 2.0, Jan. 1997

July 1997

Rev. B, June 1995

Rev. 1.0, 1997

Rel. 1.1a, Jan. '97

Iss. 2, Dec. 2000

2000

2000

3

Zarlink Semiconductor Inc.

Share Link: