CY7C0430V-100BGC データシートの表示（PDF） - Cypress Semiconductor

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CY7C0430V-100BGC

3.3V 64K x 18 Synchronous QuadPort™ Static RAM

Cypress Semiconductor 

PRELIMINARY

CY7C0430V

Functional Description

The CY7C0430V is a 1-Mb synchronous true four-port Static

RAM. This is a high-speed, low-power 3.3V CMOS dual-port

static RAM. Four ports are provided, permitting independent,

simultaneous access for reads from any location in memory. A

particular port can write to a certain location while other ports

are reading that location simultaneously. The result of writing

to the same location by more than one port at the same time

is undefined. Registers on control, address and data lines al-

low for minimal set-up and hold time.

Data is registered for decreased cycle time. Clock to data valid

tCD2 = 4.7 ns. Each port contains a burst counter on the input

address register. After externally loading the counter with the

initial address the counter will self-increment the address in-

ternally (more details to follow). The internal write pulse width

is independent of the duration of the R/W input signal. The

internal write pulse is self-timed to allow the shortest possible

cycle times.

A HIGH on CE0 or LOW on CE1 for one clock cycle will power

down the internal circuitry to reduce the static power consump-

tion. One cycle is required with chip enables asserted to reac-

tivate the outputs.

Counter enable inputs are provided to stall the operation of the

address input and utilize the internal address generated by the

internal counter for fast interleaved memory applications. A

port's burst counter is loaded with an external address when

the port's Counter Load pin (CNTLD) is asserted LOW. When

the port's Counter Increment pin (CNTINC) is asserted, the

address counter will increment on each subsequent LOW-to-

HIGH transition of that port's clock signal. This will read/write

one word from/into each successive address location until

CNTINC is deasserted. The counter can address the entire

memory array and will loop back to the start. Counter Reset

(CNTRST) is used to reset the burst counter. A counter-mask

register is used to control the counter wrap. The counter and

mask register operations are described in more details in the

following sections.

The counter or mask register values can be read back on the

bidirectional address lines by activating MKRD or CNTRD re-

spectively.

The new features added to the QuadPort™ as compared to

standard synchronous dual-ports include: readback of

burst-counter internal address value on address lines,

counter-mask registers to control the counter wrap-around,

readback of mask register value on address lines, interrupt

flags for message passing, BIST, JTAG for boundary scan, and

asynchronous Master Reset.

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