MT91L62 データシートの表示（PDF） - Zarlink Semiconductor Inc
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MT91L62 Datasheet PDF : 19 Pages
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MT91L62
Data Sheet
Electrical Characteristics† for Analog Inputs
Characteristics
Sym.
1 Maximum input voltage without
overloading Codec
across AOUT+/AOUT-
VIOLH
Min.
Typ.‡
2.128
2.20
Max.
Units
Test Conditions
Vp-p A/µ = 0
Vp-p A/µ = 1
2 Input Impedance
ZI
50
kΩ Ain+/Ain- to VSS
† Electrical Characteristics are over recommended temperature range & recommended power supply voltages.
‡ Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing.
AC Electrical Characteristics† - SSI BUS Synchronous Timing (see Figure 5)
Characteristics
Sym. Min. Typ.‡ Max. Units
Test Conditions
1 BCL Clock Period
tBCL 244
1953 ns BCL=4096 kHz to 512 kHz
2 BCL Pulse Width High
tBCLH 115
122
ns BCL=4096 kHz
3 BCL Pulse Width Low
tBCLL
122
ns BCL=4096 kHz
4 BCL Rise/Fall Time
tR/tF
20
ns Note 1
5 Strobe Pulse Width
tENW
8 x tBCL
ns Note 1
6 Strobe setup time before BCL falling tSSS 70
tBCL-80 ns
7 Strobe hold time after BCL falling
tSSH
80
tBCL-80 ns
8 Dout High Impedance to Active Low tDOZL
from Strobe rising
55
ns CL=50 pF, RL=1K
9 Dout High Impedance to Active High tDOZH
from Strobe rising
55
ns CL=50 pF, RL=1K
10 Dout Active Low to High Impedance tDOLZ
from Strobe falling
90
ns CL=50 pF, RL=1K
11 Dout Active High to High Impedance tDOHZ
from Strobe falling
90
ns CL=50 pF, RL=1K
12 Dout Delay (high and low) from BCL tDD
rising
80
ns CL=50 pF, RL=1K
13 Din Setup time before BCL falling
tDIS
10
ns
14 Din Hold Time from BCL falling
tDIH
50
ns
† Timing is over recommended temperature range & recommended power supply voltages.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
NOTE 1: Not production tested, guaranteed by design.
11
Zarlink Semiconductor Inc.
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