IS61NW6432 データシートの表示（PDF） - Integrated Silicon Solution
部品番号
コンポーネント説明
メーカー
IS61NW6432 Datasheet PDF : 13 Pages
| |||
IS61NW6432
TRUTH TABLE(1)
Operation
Address
Used
R/W
CEx ADV/LD CEN BWx
CLK
Begin New Write Cycle
External
L
L
L
L
Valid
L-H
Begin New Read Cycle
External
H
L
L
L
X
L-H
Advance Burst Counter(2)
(Burst Write)
Internal
X
X
H
L
Valid
L-H
Advance Burst Counter
(Burst Read)
Internal
X
X
H
L
X
L-H
Deselect (2 Cycle)(3)
X
X
H
L
L
X
L-H
Hold/NOOP(4)
X
X
X
X
H
X
L-H
Notes:
1. "X" Means don't care.
2. When ADV/LD signal is sampled HIGH, the internal burst counter is incremented. The R/W signal is ignored when the
counter is advanced. Therefore, the nature of the burst cycle (Read or Write) is determined by the status of the R/W signal
when the first address is loaded at the beginning of the burst cycle.
3. Deselect cycle is initiated when CEx is sampled HIGH and ADV/LD sampled LOW at rising edge of clock. The data bus will
tri-state two cycles after deselect is initiated.
4. When CEN is sampled high at the rising edge of clock, that clock edge is blocked from propogating through the part.
The state of all the internal registers remains unchanged.
PARTIAL TRUTH TABLE (Non-burst)
Function
Read
Write Byte 1
Write Byte 2
Write Byte 3
Write Byte 4
Write All Bytes
R/W BW1 BW2 BW3 BW4 CEx ADV/LD
H
X
X
X
X
L
L
L
L
H
H
H
L
L
L
H
L
H
H
L
L
L
H
H
L
H
L
L
L
H
H
H
L
L
L
L
L
L
L
L
L
L
FUNCTIONAL TIMING DIAGRAM
CYCLE
CLOCK
ADDRESS
(A0-A15)
CONTROL
(BWx, R/W, ADV/LD)
n+29
A29
C29
n+30
A30
C30
DATA
(I/O1-I/O32)
D27 D28
n+31
A31
C31
D29
n+32
A32
C32
D30
n+33
A33
C33
D31
n+34 n+35 n+36 n+37
A34
A35
A36
A37
C34 C35 C36 C37
D32 D33 D34 D35
4
Integrated Silicon Solution, Inc.
ADVANCE INFORMATION SR050-0B
07/15/98
Share Link: 