IS61NW6432
TYPICAL OPERATION (CE1, CE3 and CEN are LOW, CE2 is HIGH, Non-Burst Operation)
Cycle Address
R/W ADV/LD CEx CEN BWx OE I/O
n
A0
H
L
L
L
X
?
D–2
n+1
A1
L
L
L
L
L
?
D–1
n+2
A2
H
L
L
L
X
L
D0
n+3
A3
L
L
L
L
L
X
D1
n+4
A4
H
L
L
L
X
L
D2
n+5
A5
L
L
L
L
L
X
D3
n+6
A6
H
L
L
L
X
L
D4
n+7
A7
L
L
L
L
L
X
D5
n+8
A8
H
L
L
L
X
L
D6
n+9
A9
L
L
L
L
L
X
D7
n+10
A10
H
L
L
L
X
L
D8
n+11
A11
H
L
L
L
X
X
D9
n+12
A12
L
L
L
L
L
L
D10
n+13
A13
L
L
L
L
L
L
D11
n+14
A14
H
L
L
L
X
X
D12
n+15
A15
H
L
L
L
X
X
D13
n+16
A16
H
L
L
L
X
L
D14
n+17
A17
L
L
L
L
L
L
D15
n+18
A18
L
L
L
L
L
L
D16
n+19
A19
L
L
L
L
L
X
D17
n+20
A20
H
L
L
L
X
X
D18
n+21
A21
H
L
L
L
X
Note:
1. H = High; L = Low; X = Don't Care; ? = Don't Know; Z = High Impedance
X
D19
Comments
?
?
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Integrated Silicon Solution, Inc.
5
ADVANCE INFORMATION SR050-0B
07/15/98