HM5164165LJ-5 データシートの表示（PDF） - Hitachi -> Renesas Electronics
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HM5164165LJ-5 Datasheet PDF : 36 Pages
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HM5164165 Series, HM5165165 Series
16. tRASP defines RAS pulse width in EDO page mode cycles.
17. Access time is determined by the longest among tAA, tCAC and tCPA.
18. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to
the device.
19. When output buffers are enabled once, sustain the low impedance state until valid data is obtained.
When output buffer is turned on and off within a very short time, generally it causes large VCC/VSS
line noise, which causes to degrade VIH min/VIL max level.
20. tHPC (min) can be achieved during a series of EDO page mode write cycles or EDO page mode read
cycles. If both write and read operation are mixed in a EDO page mode RAS cycle (EDO page
mode mix cycle (1), (2)), minimum value of CAS cycle (tCAS + tCP + 2 tT) becomes greater than the
specified tHPC (min) value.The value of CAS cycle time of mixed EDO page mode is shown in EDO
page mode mix cycle (1) and (2).
21. Data output turns off and becomes high impedance from later rising edge of RAS and CAS. Hold
time and turn off time are specified by the timing specifications of later rising edge of RAS and CAS
between tOHR and tOH, and between tOFR and tOFF.
22. tDOH defines the time at which the output level go cross. VOL = 0.8 V, VOH = 2.0 V of output timing
reference level.
23. Before and after self refresh mode, execute CBR refresh to all refresh addresses in or within 64 ms
period on the condition a and b below.
a. Enter self refresh mode within 15.6 µs after either burst refresh or distributed refresh at equal
interval to all refresh addresses are completed.
b. Start burst refresh or distributed refresh at equal interval to all refresh addresses within
15.6µs after exiting from self refresh mode.
24. In case of entering from RAS-only-refresh, it is necessary to execute CBR refresh before and after
self refresh mode according as note 23.
25. For L-version, it is available to apply each 128 ms and 31.2 µs instead of 64 ms and 15.6 µs at
note 23.
26 At tRASS > 100 µs, self refresh mode is activated, and not activated at tRASS < 10 µs. It is undefined
within the range of 10 µs t RASS 100 µs. For tRASS 10 µs, it is necessary to satisfy tRPS.
27. When both UCAS and LCAS go low at the same time, all 16-bit data are written into the device.
UCAS and LCAS cannot be staggered within the same write/read cycles.
28. tASC, tCAH, tRCS, tWCS, tWCH, tCSR and tRPC are determined by the earlier falling edge of UCAS or LCAS.
29. tCRP, tCHR, tRCH, tCPA and tCPW are determined by the later rising edge of UCAS or LCAS.
30. tCWL, tDH, tDS and tCHS should be satisfied by both UCAS and LCAS.
31. tCP is determined by the time that both UCAS and LCAS are high.
32. XXX: H or L (H: VIH (min) V IN V IH (max), L: VIL (min) V IN V IL (max))
///////: Invalid Dout
When the address, clock and input pins are not described on timing waveforms, their pins must be
applied VIH or VIL.
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