VSC6464 データシートの表示（PDF） - Vitesse Semiconductor

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VSC6464

64x64 Crosspoint Switch

Vitesse Semiconductor 

64x64 Crosspoint Switch

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SEMICONDUCTOR CORPORATION

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VSC6464

Figure 3 VSC6464 Asynchronous Timing Diagram

TPW

DIN<63:0>

TAMX

DOUT<63:0>

TAMN TASKW

Table 3: VSC6464 Asynchronous Timing Table

Parameters

Description

Min

Typ

Max

Units

TPW

Minimum DIN<63:0> pulse width, 50% input

1.25

-

-

ns

TAMX

DIN<63:0> to DOUT<63:0> propagation delay

-

-

6.5

ns

TAMN

DIN<63:0> to DOUT<63:0> propagation delay

2.2

-

-

ns

TASKW

DOUT<63:0> asynchronous mode data skew (any input

to any output, add 0.1 for SSO)

-

-

1.4

ns

TASKW

DOUT<63:0> asynchronous mode data skew (broadcast,

add 0.1 for SSO)

-

-

Duty Cycle Distortion, @500Mb/s(1)

-

-

0.75

ns

-

25

%

Note: 1.) Duty cycle distortion = (duty cycle in - duty cyle out)/duty cycle in * 100%, measured with a 2ns pulse width.

Figure 4 VSC6464 Synchronous Data Input Timing Diagram

CKI

DIN<63:0>

TINSU TINH

Table 4: VSC6464 Synchronous Data Input Timing Table

Parameters

FMAX

TINSU

TINH

Description

Maximum CKI frequency, 50% input

DIN<63:0> data setup time with respect to CKI

DIN<63:0> data hold time with respect to CKI

Min

Typ

Max

Units

-

-

250

MHz

0.5

-

-

ns

0.4

-

-

ns

Page 4

© VITESSE SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

G52219-0, Rev. 2.0

8/4/98

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