CY7C4201(2010) データシートの表示（PDF） - Cypress Semiconductor
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CY7C4201 Datasheet PDF : 20 Pages
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CY7C4421/4201/4211/4221 CY7C4231/4241/425164/256/512/1K/2K/4K/8K x 9
Synchronous FIFOs
CY7C4421/4201/4211/4221
CY7C4231/4241/4251
64/256/512/1K/2K/4K/8K x 9
Synchronous FIFOs
Features
■ High speed, low power, First-In First-Out (FIFO) memories
❐ 64 × 9 (CY7C4421)
❐ 256 × 9 (CY7C4201)
❐ 512 × 9 (CY7C4211)
❐ 1K × 9 (CY7C4221)
❐ 2K × 9 (CY7C4231)
❐ 4K × 9 (CY7C4241)
❐ 8K × 9 (CY7C4251)
■ High speed 100 MHz operation (10 ns read/write cycle time)
■ Low power (ICC = 35 mA)
■ Fully asynchronous and simultaneous read and write operation
■ Empty, Full, and Programmable Almost Empty and Almost Full
status flags
■ TTL-compatible
■ Expandable in width
■ Output Enable (OE) pin
■ Independent read and write enable pins
■ Center power and ground pins for reduced noise
■ Width-expansion capability
■ Space saving 7 mm × 7 mm 32-pin TQFP
■ Pin-compatible and functionally equivalent to IDT72421,
72201, 72211, 72221, 72231, and 72241
■ Pb-free Packages Available
Functional Description
The CY7C42X1 are high speed, low power FIFO memories with
clocked read and write interfaces. All are 9 bits wide. The
CY7C42X1 are pin-compatible to IDT722X1. Programmable
features include Almost Full/Almost Empty flags. These FIFOs
provide solutions for a wide variety of data buffering needs,
including high speed data acquisition, multiprocessor interfaces,
and communications buffering.
These FIFOs have 9-bit input and output ports that are controlled
by separate clock and enable signals. The input port is controlled
by a free-running clock (WCLK) and two write-enable pins
(WEN1, WEN2/LD).
When WEN1 is LOW and WEN2/LD is HIGH, data is written into
the FIFO on the rising edge of the WCLK signal. While WEN1,
WEN2/LD is held active, data is continually written into the FIFO
on each WCLK cycle. The output port is controlled in a similar
manner by a free-running read clock (RCLK) and two
read-enable pins (REN1, REN2). In addition, the CY7C42X1 has
an output enable pin (OE). The Read (RCLK) and Write (WCLK)
clocks can be tied together for single-clock operation or the two
clocks can run independently for asynchronous read/write appli-
cations. Clock frequencies up to 100 MHz are achievable.
Depth expansion is possible using one enable input for system
control, while the other enable is controlled by expansion logic to
direct the flow of data.
Logic Block Diagram
D0 - 8
INPUT
REGISTER
WCLK WEN1 WEN2/LD
Write
CONTROL
Write
POINTER
Dual Port
RAM Array
64 x 9
8k x 9
FLAG
PROGRAM
REGISTER
FLAG
LOGIC
Read
POINTER
EF
PAE
PAF
FF
RS
RESET
LOGIC
THREE-STATE
OUTPUT REGISTER
OE
Q0 - 8
Read
CONTROL
RCLK REN1 REN2
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 38-06016 Rev. *D
• San Jose, CA 95134-1709 • 408-943-2600
Revised February 4, 2010
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