CY7C4201(2010) データシートの表示（PDF） - Cypress Semiconductor

部品番号

コンポーネント説明

メーカー

CY7C4201
(Rev.:2010)

64/256/512/1K/2K/4K/8K x 9 Synchronous FIFOs

Cypress Semiconductor 

CY7C4421/4201/4211/4221

CY7C4231/4241/4251

Table 1. Pin Definitions (continued)

Pin

RCLK

Name

Read Clock

I/O

Description

I The rising edge clocks data out of the FIFO when REN1 and REN2 are LOW and the

FIFO is not Empty. When WEN2/LD is LOW, RCLK reads data out of the programmable

flag-offset register.

EF

Empty Flag

O When EF is LOW, the FIFO is empty. EF is synchronized to RCLK.

FF

Full Flag

O When FF is LOW, the FIFO is full. FF is synchronized to WCLK.

PAE

Programmable

O When PAE is LOW, the FIFO is almost empty based on the almost empty offset value

Almost Empty

programmed into the FIFO.

PAF

Programmable

O When PAF is LOW, the FIFO is almost full based on the almost full offset value

Almost Full

programmed into the FIFO.

RS

Reset

I Resets device to empty condition. A reset is required before an initial read or write

operation after power up.

OE

Output Enable

I When OE is LOW, the FIFO’s data outputs drive the bus to which they are connected.

If OE is HIGH, the FIFO’s outputs are in High-Z (high-impedance) state.

Document #: 38-06016 Rev. *D

Page 4 of 20

[+] Feedback

Share Link: