CY7C4231-25JC データシートの表示（PDF） - Cypress Semiconductor
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CY7C4231-25JC Datasheet PDF : 21 Pages
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CY7C4421/4201/4211/4221
CY7C4231/4241/4251
Switching Waveforms (continued)
Write Programmable Registers
tCLKH
tCLK
tCLKL
WCLK
WEN2/LD
tENS
tENH
WEN1
tENS
tDS
tDH
D0 –D8
PAE OFFSET
LSB
PAE OFFSET
MSB
PAF OFFSET
LSB
PAF OFFSET
MSB
42X1–14
Read Programmable Registers
tCLKH
tCLK
RCLK
WEN2/LD
tENS
REN1,
REN2
tENS
Q0 –Q8
tCLKL
tENH
tA
UNKNOWN
PAF OFFSET
MSB
PAE OFFSET LSB
PAE OFFSET MSB
PAF OFFSET
LSB
42X1–15
Architecture
The CY7C42X1 consists of an array of 64 to 8K words of 9 bits
each (implemented by a dual-port array of SRAM cells), a read
pointer, a write pointer, control signals (RCLK, WCLK, REN1,
REN2, WEN1, WEN2, RS), and flags (EF, PAE, PAF, FF).
Resetting the FIFO
Upon power-up, the FIFO must be reset with a Reset (RS)
cycle. This causes the FIFO to enter the Empty condition sig-
nified by EF being LOW. All data outputs (Q0–8) go LOW tRSF
after the rising edge of RS. In order for the FIFO to reset to its
default state, a falling edge must occur on RS and the user
must not read or write while RS is LOW. All flags are guaran-
teed to be valid tRSF after RS is taken LOW.
FIFO Operation
When the WEN1 signal is active LOW and WEN2 is active HIGH,
data present on the D0–8 pins is written into the FIFO on each
rising edge of the WCLK signal. Similarly, when the REN1 and
REN2 signals are active LOW, data in the FIFO memory will
be presented on the Q0–8 outputs. New data will be presented
on each rising edge of RCLK while REN1 and REN2 are ac-
tive. REN1 and REN2 must set up tENS before RCLK for it to
be a valid read function. WEN1 and WEN2 must occur tENS
before WCLK for it to be a valid write function.
An output enable (OE) pin is provided to three-state the Q0–8
outputs when OE is asserted. When OE is enabled (LOW),
data in the output register will be available to the Q0–8 outputs
after tOE.
The FIFO contains overflow circuitry to disallow additional
writes when the FIFO is full, and underflow circuitry to disallow
additional reads when the FIFO is empty. An empty FIFO
maintains the data of the last valid read on its Q0–8 outputs
even after additional reads occur.
Write Enable 1 (WEN1) - If the FIFO is configured for pro-
grammable flags, Write Enable 1 (WEN1) is the only write en-
able control pin. In this configuration, when Write Enable 1
12
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