CY7C4231-25JC データシートの表示（PDF） - Cypress Semiconductor
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CY7C4231-25JC Datasheet PDF : 21 Pages
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CY7C4421/4201/4211/4221
CY7C4231/4241/4251
(WEN1) is LOW, data can be loaded into the input register and
RAM array on the LOW-to-HIGH transition of every write clock
(WCLK). Data is stored is the RAM array sequentially and in-
dependently of any on-going read operation.
Write Enable 2/Load (WEN2/LD) - This is a dual-purpose pin.
The FIFO is configured at Reset to have programmable flags
or to have two write enables, which allows for depth expansion.
If Write Enable 2/Load (WEN2/LD) is set active HIGH at Reset
(RS=LOW), this pin operates as a second write enable pin.
If the FIFO is configured to have two write enables, when Write
Enable (WEN1) is LOW and Write Enable 2/Load (WEN2/LD)
is HIGH, data can be loaded into the input register and RAM
array on the LOW-to-HIGH transition of every write clock
(WCLK). Data is stored in the RAM array sequentially and in-
dependently of any on-going read operation.
Programming
When WEN2/LD is held LOW during Reset, this pin is the load
(LD) enable for flag offset programming. In this configuration,
WEN2/LD can be used to access the four 8-bit offset registers
contained in the CY7C42X1 for writing or reading data to these
registers.
When the device is configured for programmable flags and
both WEN2/LD and WEN1 are LOW, the first LOW-to-HIGH
transition of WCLK writes data from the data inputs to the emp-
ty offset least significant bit (LSB) register. The second, third,
and fourth LOW-to-HIGH transitions of WCLK store data in the
empty offset most significant bit (MSB) register, full offset LSB
register, and full offset MSB register, respectively, when
WEN2/LD and WEN1 are LOW. The fifth LOW-to-HIGH tran-
sition of WCLK while WEN2/LD and WEN1 are LOW writes
data to the empty LSB register again. Figure 1 shows the reg-
isters sizes and default values for the various device types.
It is not necessary to write to all the offset registers at one time.
A subset of the offset registers can be written; then by bringing
the WEN2/LD input HIGH, the FIFO is returned to normal read
and write operation. The next time WEN2/LD is brought LOW,
a write operation stores data in the next offset register in se-
quence.
The contents of the offset registers can be read to the data
outputs when WEN2/LD is LOW and both REN1 and REN2
are LOW. LOW-to-HIGH transitions of RCLK read register con-
tents to the data outputs. Writes and reads should not be pre-
formed simultaneously on the offset registers.
64 x 9
256 x 9
512 x 9
1K x 9
8
65
0
8
7
0
8
7
0
8
7
0
Empty Offset (LSB) Reg.
Default Value = 007h
Empty Offset (LSB) Reg.
Default Value = 007h
Empty Offset (LSB) Reg.
Default Value = 007h
Empty Offset (LSB) Reg.
Default Value = 007h
8
0
8
0
8
1
0
8
1
0
(MSB)
0
(MSB)
00
8
65
0
Full Offset (LSB) Reg
Default Value = 007h
8
0
8
7
0
Full Offset (LSB) Reg
Default Value = 007h
8
0
8
7
0
Full Offset (LSB) Reg
Default Value = 007h
8
1
0
(MSB)
0
8
7
0
Full Offset (LSB) Reg
Default Value = 007h
8
1
0
(MSB)
00
2K x 9
8
7
0
Empty Offset (LSB) Reg.
Default Value = 007h
4K x 9
8
7
0
Empty Offset (LSB) Reg.
Default Value = 007h
8K x 9
8
7
0
Empty Offset (LSB) Reg.
Default Value = 007h
8
2
0
8
3
0
8
4
0
(MSB)
000
(MSB)
0000
(MSB)
00000
8
7
0
Full Offset (LSB) Reg
Default Value = 007h
8
7
0
Full Offset (LSB) Reg
Default Value = 007h
8
7
0
Full Offset (LSB) Reg
Default Value = 007h
8
2
0
8
3
0
8
4
0
(MSB)
000
(MSB)
0000
(MSB)
00000
Figure 1. Offset Register Location and Default Values
13
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