CY7C4231-25JC データシートの表示（PDF） - Cypress Semiconductor
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CY7C4231-25JC Datasheet PDF : 21 Pages
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241/42
fax id: 5409
CY7C4421/4201/4211/4221
CY7C4231/4241/4251
64/256/512/1K/2K/4K/8K x 9 Synchronous FIFOs
Features
Functional Description
• High-speed, low-power, first-in, first-out (FIFO)
memories
• 64 x 9 (CY7C4421)
• 256 x 9 (CY7C4201)
• 512 x 9 (CY7C4211)
• 1K x 9 (CY7C4221)
• 2K x 9 (CY7C4231)
• 4K x 9 (CY7C4241)
• 8K x 9 (CY7C4251)
• High-speed 100-MHz operation (10 ns read/write cycle
time)
• Low power (ICC = 35 mA)
• Fully asynchronous and simultaneous read and write
operation
• Empty, Full, and Programmable Almost Empty and
Almost Full status flags
• TTL- compatible
• Expandable in width
• Output Enable (OE) pin
• Independant read and write enable pins
• Center power and ground pins for reduced noise
• Width Expansion Capability
• Space saving 7mm x 7mm 32-pin TQFP
• 32-pin PLCC
• Pin compatible and functionally equivalent to IDT72421,
72201, 72211, 72221, 72231, 72241
THe CY7C42X1 are high-speed, low-power, first-in first-out
(FIFO) memories with clocked read and write interfaces. All
are 9 bits wide. The CY7C42X1 are pin-compatible to
IDT722X1. Programmable features include Almost Full/Almost
Empty flags. These FIFOs provide solutions for a wide variety
of data buffering needs, including high-speed data acquisition,
multiprocessor interfaces, and communications buffering.
These FIFOs have 9-bit input and output ports that are con-
trolled by separate clock and enable signals. The input port is
controlled by a free-running clock (WCLK) and two write-en-
able pins (WEN1, WEN2/LD).
When WEN1 is LOW and WEN2/LD is HIGH, data is written
into the FIFO on the rising edge of the WCLK signal. While
WEN1, WEN2/LD is held active, data is continually written into
the FIFO on each WCLK cycle. The output port is controlled in
a similar manner by a free-running read clock (RCLK) and two
read-enable pins (REN1, REN2). In addition, the CY7C42X1
has an output enable pin (OE). The read (RCLK) and write
(WCLK) clocks may be tied together for single-clock operation
or the two clocks may be run independently for asynchronous
read/write applications. Clock frequencies up to 100 MHz are
achievable.
Depth expansion is possible using one enable input for system
control, while the other enable is controlled by expansion logic
to direct the flow of data.
Logic Block Diagram
D0 - 8
INPUT
REGISTER
WCLKWEN1 WEN2/LD
WRITE
CONTROL
WRITE
POINTER
Dual Port
RAM Array
64 x 9
8k x 9
Pin Configuration
PLCC
Top View
FLAG
PROGRAM
REGISTER
EF
FLAG
PAE
LOGIC
PAF
FF
READ
POINTER
D1
D0
PAF
PAE
GND
REN1
RCLK
REN2
OE
4 3 2 1 323130
5
29
6
28
7
27
8
26
9
25
10
24
11
23
12
22
13
21
141516171819 20
RS
WEN1
WCLK
WEN2/LD
VCC
Q8
Q7
Q6
Q5
42X1–2
TQFP
Top View
RS
RESET
LOGIC
THREE-STATE
OUTPUTREGISTER
OE
Q0 - 8
READ
CONTROL
RCLK REN1 REN2
42X1–1
D1
D0
PAF
PAE
GND
REN1
RCLK
REN2
32 31 30 29 28 27 26 25
1
24 WEN1
2
23 WCLK
3
22
WEN2/LD
4
21
VCC
5
20
Q8
6
19
Q7
7
18
Q6
8
17
Q5
9 10 11 12 13 14 15 16
42X1–3
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
March 1995 – Revised September 30, 1997
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