CY7C4231-25JC データシートの表示（PDF） - Cypress Semiconductor

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CY7C4231-25JC

64/256/512/1K/2K/4K/8K x 9 Synchronous FIFOs

Cypress Semiconductor 

CY7C4421/4201/4211/4221

CY7C4231/4241/4251

Switching Waveforms (continued)

First Data Word Latency after Reset with Simultaneous Read and Write

WCLK

tDS

D0 –D8

D0 (FIRSTVALID WRITE)

D1

D2

WEN1

tENS

[16]

tFRL

WEN2

(if applicable)

RCLK

EF

REN1,

REN2

tSKEW1

tREF

tA [17]

D3

D4

tA

Q0 –Q8

OE

tOLZ

tOE

D0

D1

42X1–9

Notes:

16. When tSKEW1 > minimum specification, tFRL (maximum) = tCLK + tSKEW1. When tSKEW1 < minimum specification, tFRL (maximum) = either 2*tCLK + tSKEW1 or tCLK + tSKEW1.

The Latency Timing applies only at the Empty Boundary (EF = LOW).

17. The first word is available the cycle after EF goes HIGH, always.

8

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