MX29F022 データシートの表示（PDF） - Macronix International

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MX29F022

2M-BIT[256K x 8]CMOS FLASH MEMORY

Macronix International 

MX29F022/022NT/B

Q2:Toggle Bit II

The "Toggle Bit II" on Q2, when used with Q6, indicates

whether a particular sector is actively erasing (that is,

the Automatic Erase algorithm is in process), or whether

that sector is erase-suspended. Toggle Bit I is valid after

the rising edge of the final WE pulse in the command

sequence.

Q2 toggles when the system reads at addresses within

those sectors that have been selected for erasure. (The

system may use either OE or CE to control the read

cycles.) But Q2 cannot distinguish whether the sector

is actively erasing or is erase-suspended. Q6, by com-

parison, indicates whether the device is actively eras-

ing, or is in Erase Suspend, but cannot distinguish which

sectors are selected for erasure. Thus, both status bits

are required for sectors and mode information. Refer to

Table 4 to compare outputs for Q2 and Q6.

Reading Toggle Bits Q6/ Q2

Refer to the toggle bit algorithm for the following

discussion. Whenever the system initially begins

reading toggle bit status, it must read Q7-Q0 at least

twice in a row to determine whether a toggle bit is

toggling. Typically, the system would note and store the

value of the toggle bit after the first read. After the

second read, the system would compare the new value

of the toggle bit with the first. If the toggle bit is not

toggling, the device has completed the program or erase

operation. The system can read array data on Q7-Q0 on

the following read cycle.

However, if after the initial two read cycles, the system

determines that the toggle bit is still toggling, the

system also should note whether the value of Q5 is high

(see the section on Q5). If it is, the system should then

determine again whether the toggle bit is toggling, since

the toggle bit may have stopped toggling just as Q5 went

high. If the toggle bit is no longer toggling, the device

has successfully completed the program or erase opera-

tion. If it is still toggling, the device did not complete the

operation successfully, and the system must write the

reset command to return to reading array data.

The remaining scenario is that system initially determines

that the toggle bit is toggling and Q5 has not gone high.

The system may continue to monitor the toggle bit and

Q5 through successive read cycles, determining the

status as described in the previous paragraph.

Alternatively, it may choose to perform other system

tasks. In this case, the system must start at the

beginning of the algorithm when it returns to determine

the status of the operation (top of the toggle bit algorithm

flow chart).

Q5

Exceeded Timing Limits

Q5 will indicate if the program or erase time has

exceeded the specified limits (internal pulse count). Under

these conditions Q5 will produce a "1". This time-out con-

dition indicates that the program or erase cycle was not

successfully completed. Data Polling and Toggle Bit are

the only operating functions not of the device under this

condition.

If this time-out condition occurs during sector erase

operation, it specifies that a particular sector is bad and

it may not be reused. However, other sectors are still

functional and may be used for the program or erase

operation. The device must be reset to use other

sectors. Write the Reset command sequence to the de-

vice, and then execute program or erase command se-

quence. This allows the system to continue to use the

other active sectors in the device.

If this time-out condition occurs during the chip erase

operation, it specifies that the entire chip is bad or

combination of sectors are bad.

If this time-out condition occurs during the byte

programming operation, it specifies that the entire

sector containing that byte is bad and this sector may

not be reused, (other sectors are still functional and can

be reused).

The time-out condition may also appear if a user tries to

program a non blank location without erasing. In this

case the device locks out and never completes the

Automatic Algorithm operation. Hence, the system never

reads a valid data on Q7 bit and Q6 never stops

toggling. Once the Device has exceeded timing limits,

the Q5 bit will indicate a "1". Please note that this is not

a device failure condition since the device was

incorrectly used.

P/N:PM0556

REV. 1.3, NOV. 11, 2002

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