MX29F400CBTI-90 データシートの表示（PDF） - Macronix International

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MX29F400CBTI-90

4M-BIT [512Kx8/256Kx16] CMOS SINGLE VOLTAGE 5V ONLY BOOT SECTOR FLASH MEMORY

Macronix International 

MX29F400C T/B

AUTOMATIC PROGRAMMING

The MX29F400C T/B is byte programmable using the

Automatic Programming algorithm. The Automatic Pro-

gramming algorithm makes the external system do not

need to have time out sequence nor to verify the data

programmed. The typical chip programming time at room

temperature of the MX29F400C T/B is less than 4.5 sec-

onds.

AUTOMATIC CHIP ERASE

The entire chip is bulk erased using 10 ms erase pulses

according to MXIC's Automatic Chip Erase algorithm.

Typical erasure at room temperature is accomplished in

less than 4 second. The Automatic Erase algorithm au-

tomatically programs the entire array prior to electrical

erase. The timing and verification of electrical erase are

controlled internally within the device.

AUTOMATIC SECTOR ERASE

The MX29F400C T/B is sector(s) erasable using MXIC's

Auto Sector Erase algorithm. Sector erase modes allow

sectors of the array to be erased in one erase cycle. The

Automatic Sector Erase algorithm automatically programs

the specified sector(s) prior to electrical erase. The tim-

ing and verification of electrical erase are controlled in-

ternally within the device.

AUTOMATIC PROGRAMMING ALGORITHM

MXIC's Automatic Programming algorithm requires the

user to only write program set-up commands (including 2

unlock write cycle and A0H) and a program command

(program data and address). The device automatically

times the programming pulse width, provides the pro-

gram verification, and counts the number of sequences.

A status bit similar to Data# Polling and a status bit tog-

gling between consecutive read cycles, provide feedback

to the user as to the status of the programming opera-

tion.

dard microprocessor write timings. The device will auto-

matically pre-program and verify the entire array. Then

the device automatically times the erase pulse width,

provides the erase verification, and counts the number

of sequences. A status bit toggling between consecu-

tive read cycles provides feedback to the user as to the

status of the programming operation.

Register contents serve as inputs to an internal state-

machine which controls the erase and programming cir-

cuitry. During write cycles, the command register inter-

nally latches address and data needed for the program-

ming and erase operations. During a system write cycle,

addresses are latched on the falling edge, and data are

latched on the rising edge of WE# or CE#, whichever

happens first .

MXIC's Flash technology combines years of EPROM

experience to produce the highest levels of quality, reli-

ability, and cost effectiveness. The MX29F400C T/B elec-

trically erases all bits simultaneously using Fowler-

Nordheim tunneling. The bytes are programmed by us-

ing the EPROM programming mechanism of hot electron

injection.

During a program cycle, the state-machine will control

the program sequences and command register will not

respond to any command set. During a Sector Erase

cycle, the command register will only respond to Erase

Suspend command. After Erase Suspend is completed,

the device stays in read mode. After the state machine

has completed its task, it will allow the command regis-

ter to respond to its full command set.

AUTOMATIC ERASE ALGORITHM

MXIC's Automatic Erase algorithm requires the user to

write commands to the command register using stan-

P/N:PM1200

REV. 1.0, DEC. 20, 2005

5

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