MX98715A データシートの表示（PDF） - Macronix International
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MX98715A Datasheet PDF : 32 Pages
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MX98715A
5. 2.1 BUS MODE REGISTER ( CSR0 )
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0
TAP-Transmit Automatic Polling
ZERO-Must be zero
CAL-Cache Alignment
PBL-Programmable Burst Length
BLE-Big/Little Endian
DSL-Descriptor Skip Length
BAR-Bus Arbitration
SWR-Software Reset
Field
0
Name
SWR
1
BAR0
6:2
DSL
7
BLE
13:8 PBL
15:14 CAL
18:17 TAP
Description
Software Reset, when set, MX98715A resets all internal hardware with the exception of
the configuration area and port selection.
Internal bus arbitration scheme between receive and transmit processes.
The receive channel usually has higher priority over transmit channel when receive FIFO
is partially full to a threshold. This threshold can be selected by programming this bit. Set
for lower threshold, reset for normal threshold.
Descriptor Skip Length, specifies the number of longwords to skip between two descrip-
tors.
Big/Little Endian, set for big endian byte ordering mode, reset for little endian byte order-
ing mode, this option only applies to data buffers
Programmable Burst Length, specifies the maximum number of longwords to be trans-
ferred in one DMA transaction. default is 0 which means unlimited burst length, possible
values can be 1,2,4,8,16,32 and unlimited .
Cache Alignment, programmable address boundaries of data burst stop, MX98715A can
handle non-cache- aligned fragement as well as cache-aligned fragment efficiently.
Transmit Auto-Polling time interval, defines the time interval for MX98715A to performs
transmit poll command automatically at transmit suspended state.
TABLE 5.2.0 TRANSMIT AUTO POLLING BITS
CSR<18:17>
Time Interval
00
No transmit auto-polling, a write to CSR1 is required to poll
01
auto-poll every 200 us
10
auto-poll every 800 us
11
auto-poll every 1.6 ms
P/N:PM0537
REV. 1.2, FEB. 24, 1999
13
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