N32T1630C1CZ-70I データシートの表示（PDF） - NanoAmp Solutions, Inc.

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N32T1630C1CZ-70I

32Mb Ultra-Low Power Asynchronous CMOS Pseudo SRAM w/ Page Mode Operation (2M x 16 bit)

NanoAmp Solutions, Inc. 

NanoAmp Solutions, Inc.

FIGURE 2: Variable Address Register

N32T1630C1C

A20 - A5

A4

A3

A2

A1

A0

Array mode for ZZ

Reserved for future

Preferably set to all 0

0 = PAR mode (default)

1

1 = RMS mode

1

0

ZZ Enable/Disable

0

0 = Deep Sleep Enabled

(default for DSA device)

1 = Deep Sleep Disabled

(default for DSI device)

Array half

0 = Bottom array (default)

1 = Top array

Array section

1 = 1/4 array

0 = 1/2 array

1 = Reserved

0 = Full array

(default)

FIGURE 3: Variable Address Register (VAR) Update Timings

A0-A4

CE

WE

tCDZZ

ZZ

LB, UB

tAS

tZZWE

tWC

tAW

tWR

tWP

tLBW, UBW

FIGURE 4: Deep Sleep Mode - Entry/Exit Timings

tZZMIN

ZZ

tCDZZ

tR

CE or

LB, UB

(DOC# 14-02-005 Rev C ECN 01-0918)

11

The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.

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