PCK2000DL データシートの表示（PDF） - Philips Electronics

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PCK2000DL

CK97 (66/100MHz) System Clock Generator

Philips Electronics 

Philips Semiconductors

CK97 (66/100MHz) System Clock Generator

Product specification

PCK2000

REF(0–2) CLOCK OUTPUT (LUMP CAPACITANCE TEST LOAD = 20pF)

SYMBOL

f

THRISE (tR)

THFALL (tF)

DUTY CYCLE (tD)

THSTB (fST)

PARAMETER

Frequency, Actual

Output rise edge rate

Output fall edge rate

Duty Cycle

Frequency stabilization from Power-up (cold start)

TEST CONDITIONS

NOTES

Frequency generated

by Crystal

LIMITS

Tamb = 0°C to +70°C

MIN

MAX

14.31818

1

4

1

4

45

55

3

UNIT

MHz

ns

ns

%

ms

48MHZ(0–1) CLOCK OUTPUT (LUMP CAPACITANCE TEST LOAD = 20pF)

SYMBOL

f

fD

THRISE (tR)

THFALL (tF)

DUTY CYCLE (tD)

THSTB (fST)

PARAMETER

Frequency, Actual

Devation from 48MHz

Output rise edge rate

Output fall edge rate

Duty Cycle

Frequency stabilization from Power-up (cold start)

TEST CONDITIONS

NOTES

Determined by PLL

divider ratio

(48.008 – 48)/48

LIMITS

Tamb = 0°C to +70°C

MIN

MAX

48.008

+167

1

4

1

4

45

55

3

UNIT

MHz

ppm

ns

ns

%

ms

ALL CLOCK OUTPUTS

SYMBOL

PARAMETER

TEST CONDITIONS

NOTES

LIMITS

Tamb = 0°C to +70°C

MIN

MAX

UNIT

TPZL, TPZH

Output enable time

1.0

8.0

ns

TPLZ, TPHZ

Output disable time

1.0

8.0

ns

NOTES:

1. See Figure 3 for measure points.

2. Period, jitter, offset, and skew are measured on the rising edge @ 1.25V for 2.5V clocks and @ 1.5V for 3.3V clocks.

3. The PCICLK is the CPUCLK divided by two at CPUCLK = 66.6MHz. PCICLK is the CPUCLK divided by three at CPUCLK = 100MHz.

4. The CPUCLK must always lead the PCICLK as shown in Figure 2.

5. THKH is measured @ 2.0V as shown in Figure 4.

6. THKL is measured @ 0.4V as shown in Figure 4.

7. The time is specified from when VDDQ achieves its nominal operating level (typical condition is VDDQ = 3.3V) until the frequency output is

stable and operating within specification.

8. Defined as once the clock is at its nominal operating frequency, the adjacent period changes cannot exceed the time specified.

9. THRISE and THFALL are measured as a transition through the threshold region VOL = 0.4V and VOH = 2.0V (1mA) JEDEC specification.

10. THRISE and THFALL (48MHz, REF, PC) are measured as a transition through the threshold region VOL = 0.4V and VOH = 2.4V

1998 Sep 29

9

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