74F543 データシートの表示（PDF） - NXP Semiconductors.
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74F543 Datasheet PDF : 15 Pages
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NXP Semiconductors
74F543
Octal latched transceiver with dual enable; 3-state
VI
negative
pulse
0V
VI
positive
pulse
0V
90 %
10 %
VM
10 %
tf
tr
90 %
VM
tW
90 %
VM
10 %
tr
tf
90 %
VM
10 %
tW
001aai298
VI
G
VCC
VO
DUT
RT
a. Input pulse definition
b. Test circuit
Test data is given in Table 8.
Definitions test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 10. Load circuitry for switching times
VEXT
RL
CL
RL
mna616
Table 8.
Input
VI
3.0 V
Test data
fI
1 MHz
tW
500 ns
tr, tf
≤ 2.5 ns
Load
CL
50 pF
RL
500 Ω
VEXT
tPHL, tPLH
open
tPZH, tPHZ
open
tPZL, tPLZ
7.0 V
74F543_4
Product data sheet
Rev. 04 — 26 January 2010
© NXP B.V. 2010. All rights reserved.
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