74F543 データシートの表示（PDF） - NXP Semiconductors.
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74F543 Datasheet PDF : 15 Pages
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NXP Semiconductors
74F543
Octal latched transceiver with dual enable; 3-state
5. Pinning information
5.1 Pinning
Fig 4. Pin configuration
74F543
LEBA 1
OEBA 2
A0 3
A1 4
A2 5
A3 6
A4 7
A5 8
A6 9
A7 10
EAB 11
GND 12
24 VCC
23 EBA
22 B0
21 B1
20 B2
19 B3
18 B4
17 B5
16 B6
15 B7
14 LEAB
13 OEAB
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5.2 Pin description
Table 2. Pin description
Symbol Pin
Description
LEBA
OEBA
A0 to A7
EAB
GND
OEAB
LEAB
B0 to B7
EBA
VCC
1
B-to-A latch enable input (active LOW)
2
B-to-A output enable input (active LOW)
3, 4, 5, 6, 7, 8, 9, data input or output
10
11
A-to-B enable input (active LOW)
12
ground (0 V)
13
A-to-B output enable input (active LOW)
14
A-to-B latch enable input (active LOW)
22, 21, 20, 19, data input or output
18, 17, 16, 15
23
B-to-A enable input (active LOW)
24
positive supply voltage
Unit load
HIGH/LOW
1.0/1.0
1.0/1.0
inputs 3.5/1.0;
outputs 150/40
1.0/2.0
Load value[1]
HIGH/LOW
20 µA/0.6 mA
20 µA/0.6 mA
inputs 70 µA/0.6 mA;
outputs 3.0 mA/24 mA
20 µA/1.2 mA
1.0/1.0
20 µA/0.6 mA
1.0/1.0
20 µA/0.6 mA
inputs 3.5/1.0;
inputs 70 µA/0.6 mA;
outputs 750/106.7 outputs 15 mA/64 mA
1.0/2.0
20 µA/1.2 mA
[1] One FAST Unit Load (UL) is defined as 20 µA in HIGH state, 0.6 µA in LOW state.
74F543_4
Product data sheet
Rev. 04 — 26 January 2010
© NXP B.V. 2010. All rights reserved.
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