NB100LVEP221 データシートの表示（PDF） - ON Semiconductor
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NB100LVEP221 Datasheet PDF : 11 Pages
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NB100LVEP221
VCC0
Q5
Q5
Q4
Q4
Q3
Q3
Q2
Q2
Q1
Q1
Q0
Q0
39 38 37 36 35 34 33 32 31 30 29 28 27
40
26
41
25
42
24
43
23
44
22
45
21
46
NB100LVEP221
20
47
19
48
18
49
17
50
16
51
15
52
14
1 2 3 4 5 6 7 8 9 10 11 12 13
Q12
Q12
Q13
Q13
Q14
Q14
Q15
Q15
Q16
Q16
Q17
Q17
VCC0
All VCC, VCCO, and VEE pins must be externally connected to appropriate Power Supply to guarantee proper operation. The thermally
conductive exposed pad on package bottom (see package case drawing) must be attached to a heat−sinking conduit, capable of transfer-
ring 1.2 Watts. This exposed pad is electrically connected to VEE internally.
Table 1. PIN DESCRIPTION
Figure 1. 52−Lead LQFP Pinout (Top View)
PIN
FUNCTION
CLK0*, CLK0** ECL/PECL Differential Inputs
CLK1*, CLK1** ECL/PECL or HSTL Differential Inputs
Q0:19, Q0:19 ECL/PECL Differential Outputs
CLK_SEL*
VBB
ECL/PECL Active Clock Select Input
Reference Voltage Output
VCC/VCCO
Positive Supply
VEE***
Negative Supply
* Pins will default LOW when left open.
** Pins will default HIGH when left open.
*** The thermally conductive exposed pad on the bottom of the
package is electrically connected to VEE internally.
Table 2. FUNCTION TABLE
CLK_SEL
Active Input
CLK0
CLK0
CLK1
CLK1
CLK_SEL
0
20
Q0 − Q19
Q0 − Q19
20
1
VBB
VCC
VEE
L
CLK0, CLK0
H
CLK1, CLK1
Figure 2. Logic Diagram
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