NB100LVEP221 データシートの表示（PDF） - ON Semiconductor

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NB100LVEP221

2.5V/3.3V1:20 Differential HSTL/ECL/PECL Clock Driver

ON Semiconductor 

NB100LVEP221

900

10

9

800

8

700

7

600

6

5

500

4

400

3

2

300

1

200

0.1

0.2

0.4

0.6

0.8

0

1.0

fIN, INPUT FREQUENCY (GHz)

Figure 3. Output Voltage (VOPP)/Jitter versus Input Frequency (VCC − VEE = 3.3 V @ 255C)

VPP

VIHCMR

VCC(LVPECL)

VIH(DIFF)

VIL(DIFF)

VEE

Figure 4. LVPECL Differential Input Levels

VCCO(HSTL)

VPP

VIH(DIFF)

VX

VIL(DIFF)

VEE

Figure 5. HSTL Differential Input Levels

Q

Driver

Device

Q

Zo = 50 W

Zo = 50 W

50 W

50 W

D

Receiver

Device

D

VTT

VTT = VCC − 2.0 V

Figure 6. Typical Termination for Output Driver and Device Evaluation

(See Application Note AND8020/D − Termination of ECL Logic Devices.)

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