NB100LVEP222(2015) データシートの表示（PDF） - ON Semiconductor

部品番号

コンポーネント説明

メーカー

NB100LVEP222
(Rev.:2015)

2.5 V/3.3 V 2:1:15 Differential ECL/PECL ÷1/÷2 Clock Driver

ON Semiconductor 

VCC 1

MR 2

fsela 3

fselb 4

CLK0 5

CLK0 6

CLK_SEL 7

CLK1 8

CLK1 9

VBB 10

fselc 11

fseld 12

VEE 13

NB100LVEP222

NB100LVEP222

Exposed Pad (EP)

39 VCC0

38 Qc0

37 Qc0

36 Qc1

35 Qc1

34 Qc2

33 Qc2

32 Qc3

31 Qc3

30 VCC0

29 NC

28 NC

27 VCC0

Figure 2. QFN−52 Pinout (Top View)

Table 1. PIN DESCRIPTION

PIN

CLK0*, CLK0**

CLK1*, CLK1**

CLK_Sel*

MR*

Qa0:1, Qa0:1

Qb0:2, Qb0:2

Qc0:3, Qc0:3

Qd0:5, Qd0:5

fseln*

VBB

VCC, VCC0

VEE***

NC

FUNCTION

ECL Differential Input Clock

ECL Differential Input Clock

ECL Clock Select

ECL Master Reset

ECL Differential Outputs

ECL Differential Outputs

ECL Differential Outputs

ECL Differential Outputs

ECL 1 or 2 Select

Reference Voltage Output

Positive Supply, VCC = VCC0

Negative Supply

No Connect

* Pins will default LOW when left open.

** Pins will default HIGH when left open.

*** The thermally conductive exposed pad on the bottom of the package is

electrically connected to VEE internally.

Table 2. FUNCTION TABLE

Input

Function

L

H

MR

CLK_Sel

fseln

Active

CLK0

÷1

Reset

CLK1

÷2

www.onsemi.com

3

Share Link: