NB100LVEP224(2003) データシートの表示（PDF） - ON Semiconductor
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NB100LVEP224
(Rev.:2003)
(Rev.:2003)
ON Semiconductor
NB100LVEP224 Datasheet PDF : 10 Pages
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NB100LVEP224
VCCO
Q7
Q7
Q6
Q6
Q5
Q5
Q4
Q4
Q3
Q3
Q2
Q2
Q1
Q1
VCCO
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
49
32
50
31
51
30
52
29
53
28
54
27
55
26
56
25
NB100LVEP224
57
24
58
23
59
22
60
21
61
20
62
19
63
18
64
17
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
VCCO
Q15
Q15
Q16
Q16
Q17
Q17
Q18
Q18
Q19
Q19
Q20
Q20
Q21
Q21
VCCO
All VCC, VCCO, and VEE pins must be externally connected to appropriate Power Supply to guarantee proper operation. The thermally
conductive exposed pad on package bottom (see package case drawing) must be attached to a heat-sinking conduit, capable of transfer-
ring 1.2 Watts. This exposed pad is electrically connected to VEE internally.
Figure 1. 64-Lead LQFP Pinout (Top View)
PIN DESCRIPTION
PIN
FUNCTION
CLK0*, CLK0**
CLK1*, CLK1**
CLK_SEL*
OE*
Q0-Q23, Q0-Q23
VCC, VCCO
VEE***
ECL Differential Input Clock
ECL Differential Input Clock
ECL Input CLK Select
ECL Output Enable
ECL Differential Outputs
Positive Supply
Negative Supply
* Pins will default LOW when left open.
** Pins will default HIGH when left open.
*** The thermally conductive exposed pad on the bottom of the
package is electrically connected to VEE internally.
FUNCTION TABLE
OE (1) CLK_SEL
Q0-Q23
Q0-Q23
L
L
L
H
H
L
H
H
CLK0
CLK1
L
L
CLK0
CLK1
H
H
1. The OE (Output Enable) signal is synchronized with the
falling edge of the LVPECL_CLK signal.
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