NB6L14MNR2G データシートの表示（PDF） - ON Semiconductor
部品番号
コンポーネント説明
メーカー
NB6L14MNR2G Datasheet PDF : 10 Pages
| |||
NB6L14
Q0
Q0 Q0 VCC GND
Exposed Pad (EP)
/Q0
16 15 14 13
Q1
Q1 1
12 IN
Q1 2
11 VT
IN
VT
50 W
/Q1
/IN 50 W
Q2 3
10 VREF_AC
Q2
Q2 4
9 IN
/Q2
EN
DQ
5 678
Q3 Q3 VCC EN
Figure 2. QFN−16 Pinout
(Top View)
VREF_AC
CLK
Q3
/Q3
Figure 3. Logic Diagram
Table 1. EN TRUTH TABLE
IN
IN
EN
Q0:Q3
Q0:Q3
0
1
1
1
0
1
x
x
0
+ = On next negative transition of the input signal (IN).
x = Don’t care.
0
1
1
0
0+
1+
Table 2. PIN DESCRIPTION
Pin
Name
I/O
Description
1
Q1
LVPECL Output Non−inverted Differential Output. Typically Terminated with 50 W Resistor to
VCC–2.0 V.
2
Q1
LVPECL Output Inverted Differential Output. Typically Terminated with 50 W Resistor to VCC – 2.0 V.
3
Q2
LVPECL Output Non−inverted Differential Output. Typically Terminated with 50 W Resistor to
VCC – 2.0 V.
4
Q2
LVPECL Output Inverted Differential Output. Typically Terminated with 50 W Resistor to VCC – 2.0 V.
5
Q3
LVPECL Output Non−inverted Differential Output. Typically Terminated with 50 W Resistor to
VCC – 2.0 V.
6
Q3
LVPECL Output Inverted Differential Output. Typically Terminated with 50 W Resistor to VCC – 2.0 V.
7
VCC
−
Positive Supply Voltage
8
EN
LVTTL/LVCMOS Synchronous Output Enable. When LOW, Q outputs will go LOW and Q outputs will
go HIGH on the next negative transition of IN input. The internal DFF register is
clocked on the falling edge of IN input (see Figure 16). The EN pin has an internal
pullup resistor and defaults HIGH when left open.
9
IN
LVPECL, CML, Inverted Differential Clock Input. Internal 50 W Resistor to Termination Pin, VT.
LVDS, HSTL
10
VREF_AC
Output Voltage Reference for capacitor−coupled inputs, only.
11
VT
Internal 100 W center−tapped Termination Pin for IN and IN.
12
IN
LVPECL, CML, Non−inverted Differential Clock Input. Internal 50 W Resistor to Termination Pin, VT.
LVDS, HSTL
13
GND
−
Negative Supply Voltage
14
VCC
−
Positive Supply Voltage
15
Q0
LVPECL Output Noninverted Differential Output. Typically Terminated with 50 W Resistor to
VCC–2.0 V.
16
Q0
LVPECL Output Inverted Differential Output. Typically Terminated with 50 W Resistor to VCC–2.0 V.
−
EP
−
The Exposed Pad (EP) on the QFN−16 package bottom is thermally connected to the
die for improved heat transfer out of package. The exposed pad must be attached to
a heat−sinking conduit. The pad is not electrically connected to the die, but is
recommended to be electrically and thermally connected to GND on the PC board.
1. In the differential configuration when the input termination pin VT, is connected to a common termination voltage or left open, and if no signal
is applied on IN/IN inputs, then the device will be susceptible to self−oscillation.
http://onsemi.com
2
Share Link: 