NBSG111(2007) データシートの表示（PDF） - ON Semiconductor
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NBSG111
(Rev.:2007)
(Rev.:2007)
ON Semiconductor
NBSG111 Datasheet PDF : 11 Pages
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NBSG111
Table 1. PIN DESCRIPTION
Pin
Name
I/O
Description
A1,A7,G1,G7,C2,E6 VEE
−
Negative Supply Voltage. All VEE Pins Must be Externally Con-
nected to Power Supply to Guarantee Proper Operation.
F3,D4,B5
VCC
−
Positive Supply Voltage. All VCC Pins Must be Externally Connected
to Power Supply to Guarantee Proper Operation.
B2
VMM
−
LVCMOS Reference Voltage Output (VCC − VEE) / 2.
F6
VBB
−
ECL Reference Voltage Output
E4
VTCLK0
−
Internal 50 W Termination Pin for CLK0. See Table 4. (Note 1)
F4
CLK0 ECL, CML, LVCMOS, LVDS, Noninverted Differential Input CLK0. Internal 75 kW to VEE.
LVTTL Input
E5
VTCLK0
−
Internal 50 W Termination Pin for CLK0. See Table 4. (Note 1)
F5
CLK0 ECL, CML, LVCMOS, LVDS, Inverted Differential Input CLK0. Internal 75 kW to VEE and 36.5 kW
LVTTL Input
to VCC.
C4
VTCLK1
−
Internal 50 W Termination Pin 1. See Table 4. (Note 1)
B4
CLK1 ECL, CML, LVCMOS, LVDS, Noninverted Differential Input CLK1. Internal 75 kW to VEE.
LVTTL Input
C3
VTCLK1
−
Internal 50 W Termination Pin for CLK1. See Table 4. (Note 1)
B3
CLK1
B1,D1,F1,G3,G5,F7, Q[0:9]
D7,B7,A5,A3
C1,E1,G2,G4,G6,E7, Q[0:9]
C7,A6,A4,A2
D5
VTSEL
ECL, CML, LVCMOS, LVDS,
LVTTL Input
RSECL Output
RSECL Output
−
Inverted Differential Input CLK1. Internal 75 kW to VEE and 36.5 kW
to VCC.
Noninverted Differential Outputs [0:9]. Typically Terminated with
50 W to VTT = VCC − 1.5 V
Inverted Differential Outputs [0:9]. Typically Terminated with 50 W to
VTT = VCC − 1.5 V
Internal 50 W Termination Pin for SEL. See Table 4. (Note 1)
D6
SEL
ECL, CML, LVCMOS, LVDS, Noninverted Differential Select Logic Input. Internal 75 kW to VEE.
LVTTL Input
C5
VTSEL
−
Internal 50 W Termination Pin for SEL. See Table 4. (Note 1)
C6
SEL
ECL, CML, LVCMOS, LVDS, Inverted Differential Select Logic Input. Internal 75 kW to VEE and
LVTTL Input
36.5 kW to VCC.
D3
VTEN
−
Internal 50 W Termination Pin for EN. See Table 4. (Note 1)
D2
EN
ECL, CML, LVCMOS, LVDS, Noninverted Differential Output Enable Pin. Internal 75 kW to VEE.
LVTTL Input
E3
VTEN
−
Internal 50 W termination Pin for EN. See Table 4. (Note 1)
E2
F2,B6
EN
ECL, CML, LVCMOS, LVDS, Inverted Differential Output Enable Pin. Internal 75 kW to VEE and
LVTTL Input
36.5 kW to VCC.
NC
−
No Connect. The NC Pins are Electrically Connected to the Die and
”MUST BE” Left Open.
1. In the differential configuration when the input termination pins (VTCLK, VTDCLK) are connected to a common termination voltage and
if no signal is applied, then the device will be susceptible to self−oscillation.
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