Freescale Semiconductor, Inc.
Table 1. Truth Table
The logic state of each output pair, GDLn and GDHn (n = 1, 2, 3), is a function of its corresponding input pair, LSEn and HSEn
(n = 1, 2, 3), along with the logic states of the MODEn and PWM inputs and the internally set overtemperature shutdown (OT),
overvoltage (OV), and current limit (CL) bits provided in this table.
NORMAL OPERATION
Switching Modes
Internally Set Bits
Input Pairs
(e.g., LSE2 and HSE2)
Output Pairs
(e.g., GDL2 and GDH2)
MODE1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
MODE0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Switching Modes
OT OV CL
LSEn
HSEn
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
1
1
FAULT MODE OPERATION
Internally Set Bits
Input Pairs
(e.g., LSE2 and HSE2)
GDLn
0
0
PWM
0
0
0
PWM
0
0
0
1
0
0
PWM
1
0
GDHn
0
1
0
0
0
1
PWM
0
0
PWM
0
0
0
PWM
0
0
Output Pairs
(e.g., GDL2 and GDH2)
MODE1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
x
x
MODE0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
x
x
OT OV CL
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
x
1
x
1
x
x
LSEn
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
x
x
HSEn
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
x
x
GDLn
0
0
0
0
0
0
0
0
0
0
1
0
0
1
1
0
0
0
GDHn
0
1
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
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