NCP361(2010) データシートの表示（PDF） - ON Semiconductor

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NCP361
(Rev.:2010)

USB Positive Overvoltage Protection Controller with Internal PMOS FET and Overcurrent Protection

ON Semiconductor 

NCP361

Operation

NCP361 provides overvoltage protection for positive

voltage, up to 20 V. A PMOS FET protects the systems

(i.e.: VBUS) connected on the Vout pin, against positive

overvoltage. The Output follows the VBUS level until

OVLO threshold is overtaken.

Undervoltage Lockout (UVLO)

To ensure proper operation under any conditions, the

device has a built−in undervoltage lock out (UVLO)

circuit. During Vin positive going slope, the output remains

disconnected from input until Vin voltage is above 3.0 V

nominal. The FLAGV output is pulled to low as long as Vin

does not reach UVLO threshold. This circuit has a 70 mV

hysteresis to provide noise immunity to transient condition.

Vin (V)

20 V

OVLO

UVLO

0

Vout

OVLO

UVLO

0

Figure 20. Output Characteristic vs. Vin

Overvoltage Lockout (OVLO)

To protect connected systems on Vout pin from

overvoltage, the device has a built−in overvoltage lock out

(OVLO) circuit. During overvoltage condition (OVLO

exceeds), the output remains disabled and FLAG is tied

low, as long as the input voltage is higher than OVLO −

hysteresis. This circuit has a 100 mV hysteresis to provide

noise immunity to transient conditions.

Overcurrent Protection (OCP)

The NCP361 integrates overcurrent protection to

prevent system/battery overload or defect. The current

limit threshold is internally set at 750 mA. This value can

be changed from 150 mA to 750 mA by a metal tweak,

please contact your ON Semiconductor representative for

availability. During current fault, the internal PMOS FET

is automatically turned off (5 ms) if the charge current

exceeds Ilim. NCP361 goes into turn on and turn off mode

as long as defect is present. The internal ton delay (4 ms

typical) allows limiting thermal dissipation. The Flag pin

goes to low level when an overcurrent fault appears. That

allows the microcontroller to count defect events and turns

off the PMOS with EN pin.

Vout

Iload

Overload

Ilim

Retrieve

normal

operation

ton

Figure 21. Overcurrent Event Example

FLAG Output

NCP361 provides a FLAG output, which alerts external

systems that a fault has occurred.

This pin is tied to low as soon as: 1.2 V < Vin < UVLO,

Vin > OVLO, Icharge > Ilimit, TJ > 150°C. When NCP361

recovers normal condition, FLAG is held high. The pin is

an open drain output, thus a pull up resistor (typically 1 MW

− Minimum 10 kW) must be provided to VCC. FLAG pin is

an open drain output.

EN Input

To enable normal operation, the EN pin shall be forced

to low or connected to ground. A high level on the pin

disconnects OUT pin from IN pin. EN does not overdrive

an OVLO or UVLO fault.

Internal PMOS FET

The NCP361 includes an internal PMOS FET to protect

the systems, connected on OUT pin, from positive

overvoltage. Regarding electrical characteristics, the

RDS(on), during normal operation, will create low losses on

Vout pin, characterized by Vin versus Vout dropout.

ESD Tests

The NCP361 fully supports the IEC61000−4−2, level 4

(Input pin, 1 mF mounted on board). That means, in Air

condition, Vin has a ±15 kV ESD protected input. In

Contact condition, Vin has ±8 kV ESD protected input.

Please refer to Figure 22 to see the IEC61000−4−2

electrostatic discharge waveform.

http://onsemi.com

8

Figure 22.

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