NCP5173(2004) データシートの表示（PDF） - ON Semiconductor
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NCP5173 Datasheet PDF : 18 Pages
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NCP5173
The low frequency pole, fP1, is determined by the error
amplifier output resistance and C1 as:
fP1
+
1
2pC1RO
The first zero generated by C1 and R1 is:
fZ1
+
1
2pC1R1
The phase lead provided by this zero ensures that the loop
has at least a 45° phase margin at the crossover frequency.
Therefore, this zero should be placed close to the pole
generated in the power stage which can be identified at
frequency:
fP
+
1
2pCORLOAD
where:
CO = equivalent output capacitance of the error amplifier
≈120 pF;
RLOAD= load resistance.
The high frequency pole, fP2, can be placed at the output
filter’s ESR zero or at half the switching frequency. Placing
the pole at this frequency will cut down on switching noise.
The frequency of this pole is determined by the value of C2
and R1:
fP2
+
1
2pC2R1
One simple method to ensure adequate phase margin is to
design the frequency response with a −20 dB per decade
slope, until unity−gain crossover. The crossover frequency
should be selected at the midpoint between fZ1 and fP2 where
the phase margin is maximized.
fP1
fZ1
fP2
Frequency (LOG)
Figure 26. Bode Plot of the Compensation Network
Shown in Figure 25
VSW Voltage Limit
In the boost topology, VSW pin maximum voltage is set by
the maximum output voltage plus the output diode forward
voltage. The diode forward voltage is typically 0.5 V for
Schottky diodes and 0.8 V for ultrafast recovery diodes:
VSW(MAX) + VOUT(MAX))VF
where:
VF = output diode forward voltage.
In the flyback topology, peak VSW voltage is governed by:
VSW(MAX) + VCC(MAX))(VOUT)VF) N
where:
N = transformer turns ratio, primary over secondary.
When the power switch turns off, there exists a voltage
spike superimposed on top of the steady−state voltage.
Usually this voltage spike is caused by transformer leakage
inductance charging stray capacitance between the VSW and
PGND pins. To prevent the voltage at the VSW pin from
exceeding the maximum rating, a transient voltage
suppressor in series with a diode is paralleled with the
primary windings. Another method of clamping switch
voltage is to connect a transient voltage suppressor between
the VSW pin and ground.
Magnetic Component Selection
When choosing a magnetic component, one must consider
factors such as peak current, core and ferrite material, output
voltage ripple, EMI, temperature range, physical size and
cost. In boost circuits, the average inductor current is the
product of output current and voltage gain (VOUT/VCC),
assuming 100% energy transfer efficiency. In continuous
conduction mode, inductor ripple current is:
IRIPPLE
+
VCC(VOUT * VCC)
(f)(L)(VOUT)
where:
f = 560 kHz
The peak inductor current is equal to average current plus
half of the ripple current, which should not cause inductor
saturation. The above equation can also be referenced when
selecting the value of the inductor based on the tolerance of
the ripple current in the circuits. Small ripple current
provides the benefits of small input capacitors and greater
output current capability. A core geometry like a rod or
barrel is prone to generating high magnetic field radiation,
but is relatively cheap and small. Other core geometries,
such as toroids, provide a closed magnetic loop to prevent
EMI.
Input Capacitor Selection
In boost circuits, the inductor becomes part of the input
filter, as shown in Figure 28. In continuous mode, the input
current waveform is triangular and does not contain a large
pulsed current, as shown in Figure 27. This reduces the
requirements imposed on the input capacitor selection.
During continuous conduction mode, the peak to peak
inductor ripple current is given in the previous section. As
we can see from Figure 27, the product of the inductor
current ripple and the input capacitor’s effective series
resistance (ESR) determine the VCC ripple. In most
applications, input capacitors in the range of 10 mF to
100 mF with an ESR less than 0.3 W work well up to a full
1.5 A switch current.
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