NCP5008DMR2(2003) データシートの表示（PDF） - ON Semiconductor

部品番号

コンポーネント説明

メーカー

NCP5008DMR2
(Rev.:2003)

Backlight LED Boost Driver

ON Semiconductor 

NCP5008, NCP5009

Remote Control Programming Sequence

tCSsetup

CS

CLEAR

CLK

Qdata

tclear

B1

B2

B3

B4

B5

B6

B7

Iout ref

Last Latched Bit

Output Current Programmed Register

Internal Latch Data and Reset

Iout

Ioutdly

Figure 19. Programming Sequence

Upon CS transition from High to Low, the internal

sequence will take place:

− Qdata is internally set to high level.

− Upon positive going transition of the next CLK signal,

the Qdata is shifted to the next Bn stage.

− Clear the Qdata flip−flop upon the positive going of

the SetReg[B1] transient.

The sequence keeps going until CS = High.

When the CS line returns to a High state, the

programming output current flip−flop is set according to

the previous state of the shift register and SetReg B[1−7] is

cleared afterward.

Depending upon the CS width, for a given CLK period,

the last SetReg bit will be latched and the output current

will be adjusted accordingly. If the number of CLK pulses

is higher than 7, the Qdata is lost and the SetReg register

bits B[1−7] are in the Low state, yielding a zero output

current.

The internal shift register can be clear by sending more

than 7 pulses to the CLK pin when the pin CS is low. If the

internal shift register is clear upon the CS transition from

Low to High, the device will be placed or maintained in the

shut down mode.

When the register content is higher than zero, the DC/DC

is activated and a 100 ms delay (typical) is necessary to

stabilize the output current to the programmed value.

http://onsemi.com

11

Share Link: