NCV7356(2004) データシートの表示（PDF） - ON Semiconductor
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NCV7356 Datasheet PDF : 14 Pages
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NCV7356
TIMING MEASUREMENT LOAD CONDITIONS
Normal and High Voltage Wake−Up Mode
min load / min tau
3.3 kohm / 540 pF
min load / max tau
3.3 kohm / 1.2 nF
max load / min tau
200 ohm / 5.0 nF
max load / max tau
200 ohm / 20 nF
High−Speed Mode
Additional 140 ohm tool resistance
to ground in parallel
Additional 120 ohm tool resistance
to ground in parallel
ELECTRICAL CHARACTERISTICS (5.0 V ≤ VBAT ≤ 27 V, −40°C ≤ TA ≤ 125°C, unless otherwise specified.)
AC CHARACTERISTICS (See Figures 2, 3, and 4)
Characteristic
Symbol
Condition
Min
Typ
Max Unit
Transmit Delay in Normal and Wake−Up
Mode, Bus Rising Edge (Note 6)
tTr
min and max loads per Page 9
2.0
Transmit Delay in Wake−Up Mode to VihWU,
tTWUr
min and max loads per Page 9
2.0
Bus Rising Edge (Note 7)
Transmit Delay in Normal Mode,
Bus Falling Edge (Note 8)
tTf
min and max loads per Page 9
1.8
Transmit Delay in Wake−Up Mode,
Bus Falling Edge (Note 8)
tTWU1f min and max loads per Page 9
3.0
Transmit Delay in High−Speed Mode,
Bus Rising Edge (Note 9)
tTHSr
min and max loads per Page 9
0.1
−
6.3
ms
−
18
ms
−
10
ms
−
13.7
ms
−
1.5
ms
Transmit Delay in High−Speed Mode,
Bus Falling Edge (Note 10)
tTHSf
min and max loads per Page 9
0.1
−
3.0
ms
Receive Delay, All Active Modes (Note 11)
tDR
CANH High to Low Transition
0.3
−
Receive Delay, All Active Modes (Note 11)
tRD
CANH Low to High Transition
0.3
−
Input Minimum Pulse Length,
All Active Modes (Note 11)
tmpDR CANH High to Low Transition
0.15
−
tmpRD
CANH Low to High Transition
0.15
−
Wake−Up Filter Time Delay
tWUF
See Figure 3
10
−
Receive Blanking Time
After TxD L−H Transition
trb
See Figure 4
0.5
−
1.0
ms
1.0
ms
1.0
ms
1.0
70
ms
6.0
ms
TxD Timeout Reaction Time
TxD Timeout Reaction Time
Delay from Normal to High−Speed and
High Voltage Wake−Up Mode
ttout
Normal and High−Speed Mode
−
ttoutwu Wake−Up Mode
−
tdnhs
−
−
20
−
ms
30
−
ms
−
30
ms
Delay from High−Speed and High Voltage
tdhsn
−
Wake−Up to Normal Mode
−
−
30
ms
Delay from Normal to Standby Mode
tdsby
VBAT = 6.0 V to 27 V
−
−
500
ms
Delay from Sleep to Normal Mode
tdsnwu
VBAT = 6.0 V to 27 V
−
−
50
ms
Delay from Standby to Sleep Mode
tdsleep
VBAT = 6.0 V to 27 V
100
250
1000 ms
6. The maximum signal delay time for a bus rising edge is measured from Vcmos_il on the TxD input pin to the VihMax + Vgoff max level on CANH
at maximum network time constant, minimum signal delay time for a bus rising edge is measured from Vcmos_ih on the TxD input pin to 1 V
on CANH at minimum network time constant. These definitions are valid in both normal and High Voltage Wake−Up (HVWU) mode.
7. The maximum signal delay time for a bus rising edge in HVWU mode is measured from Vcmos_il on the TxD input pin to the VihWuMax + Vgoff
max level on CANH at maximum network time constant, minimum signal delay time for a bus rising edge is measured from Vcmos_ih on the
TxD input pin to 1 V on CANH at minimum network time constant.
8. Maximum signal delay time for a bus falling edge is measured from Vcmos_ih on the TxD input pin to 1 V on CANH at maximum network time
constant, minimum signal delay time for a bus falling edge is measured from Vcmos_ih on the TxD input pin to the VihMax + Vgoff max level on
CANH. These definitions are valid in both normal and HVWU mode.
9. The signal delay time in high−speed mode for a bus rising edge is measured from Vcmos_il on the TxD input pin to the VihMax + Vgoff max level
on CANH at maximum high−speed network time constant.
10. The signal delay time in high−speed mode for a bus falling edge is measured from Vcmos_ih on the TxD input pin to 1 V on CANH at maximum
high−speed network time constant.
11. Receive delay time is measured from the rising / falling edge crossing of the nominal Vih value on CANH to the falling (Vcmos_il_max) / rising
(Vcmos_ih_min) edge of RxD. This parameter is tested by applying a square wave signal to CANH. The minimum slew rate for the bus rising
and falling edges is 50 V/ms. The low level on bus is always 0V. For normal mode and high−speed mode testing the high level on bus is 4 V.
For HVWU mode testing the high level on bus is VBAT − 2 V.
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