NCV70501 データシートの表示（PDF） - ON Semiconductor

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NCV70501

Micro-Stepping Motor Driver

ON Semiconductor 

NCV70501

Automatic Duty Cycle Adaptation

If during regulation the set point current is not reached

before 75% of Tpwm, the duty cycle of the PWM is adapted

automatically to > 50% (top regulation) to maintain the

requested average current in the coils. This process is

completely automatic and requires no additional parameters

for operation. The state of the duty cycle adaptation mode is

represented in the T/B bits of the appropriate status registers

for both motor windings X and Y. Figure 7 gives a

representation of the duty cycle adaptation.

|Icoil|

Duty Cycle

< 50%

Duty Cycle > 50%

Duty Cycle < 50%

Actual value

Set value

0

TPWM

Bit T/B

Bottom reg. Bit T/B = 0

Top reg. Bit T/B = 1

Bottom reg Bit T/B = 0

Figure 7. Automatic Duty Cycle Adaptation

Step Translator

Step Mode

The step translator provides the control of the motor by

means of SPI register step mode: SM[2:0], SPI bits DIRP,

RHBP and input pins DIR (direction of rotation), RHB

(run/hold of motor) and NXT (next pulse). It is translating

consecutive steps in corresponding currents in both motor

coils for a given step mode.

One out of six possible stepping modes can be selected

through SPI−bits SM[2:0]. After power−on or hard reset, the

coil−current translator is set to the default to 1/16

micro−stepping at position ‘8*’. When remaining in the

default step mode, subsequent translator positions are all in

the same column and increased or decreased with 1.

Table 10 lists the output current versus the translator

position.

When the micro−step resolution is reduced, then the

corresponding least−significant bits of the translator

position are set to “0”. This means that the position in the

current table moves to the right. If there is no adjacent

allowed step on the same line, then the position pointer will

also move upwards or downwards (depending on the DIR

state) in the table to arrive at the corresponding position after

one following NXT pulse when DIR is ‘1’ or after two

following next pulses when DIR = ‘0’.

When the micro−step resolution is increased, then the

corresponding least−significant bits of the translator

position are added as “0”: the micro−step position moves to

the left on the same row.

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