CLK
CSB
DI
SPI
DO
NXT
DIR
RHB
ERRB
TST
NCV70501
VBB
Timebase
Internal voltage
regulator 3.3 V
Logic &
Registers
STALL
TSD
Open /
Short
OTP
POR
Band−
gap
EMC
P
W
M
I−sense
EMC
P
W
M
I−sense
NCV70501
Figure 1. Block Diagram NCV70501
GND
Table 1. PIN LIST AND DESCRIPTION
Name
Pin
Description
DO
1
SPI data output
CSB
2
SPI chip select input
DI
3
SPI data input
GND
4
Ground
CLK
5
SPI clock input
NXT
6
Next micro−step input
DIR
7
Direction input
ERRB
8
Error Output
RHB
9
Run/Hold Current selection input
MOTYN
10
Negative end of phase Y coil output
MOTYP
11
Positive end of phase Y coil output
VBB
12
Voltage supply Input
GND
13
Ground
MOTXN
14
Negative end of phase X coil output
MOTXP
15
Positive end of phase X coil output
TST
16
Test pin input (to be tied to ground in normal operation)
MOTXP
MOTXN
MOTYP
MOTYN
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