NCV8876 データシートの表示（PDF） - ON Semiconductor

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NCV8876

Automotive Grade Start-Stop Non-Synchronous Boost Controller

ON Semiconductor 

NCV8876

THEORY OF OPERATION

ROSC

Oscillator

ROSC

PWM Comparator

SQ

R

+

CSA

Slope

Compensation

Gate

Drive

GDRV

RGDRV

ISNS

L

VIN

NRVB440FS

NVMFS5844NL

VOU-

T

CO

RL

RSNS

Voltage

Error

WAKEUP

VOUT

VEA

NCV8876

STATUS

VMI-

CRO

STATUS

Compensation

Figure 11. Current Mode Control Schematic

Regulation

The NCV8876 is a non−synchronous boost controller

designed to supply a minimum output voltage during

Start−Stop vehicle operation battery voltage sags. The

NCV8876 is in low quiescent current sleep mode under

normal battery operation (12 V) and is enabled when the

supply voltage drops below the descending threshold (7.3 V

for the NCV887600). Boost operation is initiated when the

supply voltage is below the regulation set point (6.8 V for the

NCV887600). Once the supply voltage sag condition ends

and begins to increase, the NCV8876 boost operation will

cease when the supply voltage increases beyond the

regulation set point. The NCV8876 low quiescent current

sleep mode resumes once the supply voltage increases

beyond the ascending voltage threshold (7.7 V for the

NCV887600).

The NCV8876 VOUT pin serves the dual purpose: (1)

powering the NCV8876 and (2) providing the regulation

feedback signal. The feedback network is imbedded within

the IC to eliminate the constant current battery drain that would

exist with the use of external voltage feedback resistors.

There is no soft−start operating mode. The NCV8876 will

instantly respond to a voltage sag so as to maintain normal

operation of downstream loads. Once the NCV8876 is

enabled, the voltage error operational transconductance

amplifier supplies current to set VC to 1.1 V to minimize the

feedback loop response time when the battery voltage sag

goes below the regulation set point.

Current Mode Control

The NCV8876 incorporates a current mode control

scheme, in which the PWM ramp signal is derived from the

power switch current. This ramp signal is compared to the

output of the error amplifier to control the on−time of the

power switch. The oscillator is used as a fixed−frequency

clock to ensure a constant operational frequency. The

resulting control scheme features several advantages over

conventional voltage mode control. First, derived directly

from the inductor, the ramp signal responds immediately to

line voltage changes. This eliminates the delay caused by the

output filter and the error amplifier, which is commonly

found in voltage mode controllers. The second benefit

comes from inherent pulse−by−pulse current limiting by

merely clamping the peak switching current. Finally, since

current mode commands an output current rather than

voltage, the filter offers only a single pole to the feedback

loop. This allows for a simpler compensation.

The NCV8876 also includes a slope compensation

scheme in which a fixed ramp generated by the oscillator is

added to the current ramp. A proper slope rate is provided to

improve circuit stability without sacrificing the advantages

of current mode control.

Current Limit

The NCV8876 features two current limit protections,

peak current mode and over current latch off. When the

current sense amplifier detects a voltage above the peak

current limit between ISNS and GND after the current limit

leading edge blanking time, the peak current limit causes the

power switch to turn off for the remainder of the cycle. Set

the current limit with a resistor from ISNS to GND, with R

= VCL / Ilimit.

If the voltage across the current sense resistor exceeds the

over current threshold voltage the device enters over current

hiccup mode. The device will remain off for the hiccup time

of duration 1024/fosc.

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