EVAL-AD7470CB(2000) データシートの表示（PDF） - Analog Devices

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EVAL-AD7470CB
(Rev.:2000)

1.75 MSPS, 4 mW 10-Bit/12-Bit Parallel ADCs

Analog Devices 

AD7470/AD7472

CIRCUIT DESCRIPTION

CONVERTER OPERATION

The AD7470/AD7472 is a 10-bit/12-bit successive approxima-

tion analog-to-digital converter based around a capacitive DAC.

The AD7470/AD7472 can convert analog input signals in the

range 0 V to VREF. Figure 2 shows a very simplified schematic of

the ADC. The Control Logic, SAR and the Capacitive DAC

are used to add and subtract fixed amounts of charge from

the sampling capacitor to bring the comparator back into a

balanced condition.

CAPACITIVE

DAC

COMPARATOR

VIN

VREF

SWITCHES

SAR

CONTROL

INPUTS

CONTROL LOGIC

OUTPUT DATA

10-/12-BIT PARALLEL

Figure 2. Simplified Block Diagram of AD7470/AD7472

Figure 3 shows the ADC during its acquisition phase. SW2 is

closed and SW1 is in Position A. The comparator is held in a

balanced condition and the sampling capacitor acquires the

signal on VIN.

CAPACITIVE

DAC

VIN

A

SW1 B

2k⍀

SW2

CONTROL LOGIC

AGND

COMPARATOR

Figure 3. ADC Acquisition Phase

Figure 4 shows the ADC during conversion. When conversion

starts SW2 will open and SW1 will move to position B, causing

the comparator to become unbalanced. The ADC then runs

through its successive approximation routine and brings the

comparator back into a balanced condition. When the compara-

tor is rebalanced, the conversion result is available in the SAR

register.

TYPICAL CONNECTION DIAGRAM

Figure 5 shows a typical connection diagram for the AD7470/

AD7472. Conversion is initiated by a falling edge on CONVST.

Once CONVST goes low the BUSY signal goes high, and at the

end of conversion the falling edge of BUSY is used to activate

an Interrupt Service Routine. The CS and RD lines are then

activated in parallel to read the 10- or 12-data bits. The recom-

mended REF IN voltage is 2.5 V providing an analog input

range of 0 V to 2.5 V, making the AD7470/AD7472 a unipolar

A/D. It is recommended to perform a dummy conversion after

power-up as the first conversion result could be incorrect. This

also ensures that the part is in the correct mode of operation.

The CONVST pin should not be floating when power is applied

as a rising edge on CONVST might not wake up the part.

In Figure 5 the VDRIVE pin is tied to DVDD, which results in logic

output voltage values being either 0 V or DVDD. The voltage

applied to VDRIVE controls the voltage value of the output logic

signals. For example, if DVDD is supplied by a 5 V supply and

VDRIVE by a 3 V supply, the logic output voltage levels would be

either 0 V or 3 V. This feature allows the AD7470/AD7472 to

interface to 3 V parts while still enabling the A/D to process

signals at 5 V supply.

+

10␮F

ANALOG

+

0.1␮F

SUPPLY

47␮F 2.7V–5.25V

␮C/␮P

+2.5V*

0.1␮F

1nF

10␮F

VDRIVE AVDD

DVDD

AD7470/

AD7472

REF IN

VIN

PARALLED

INTERFACE

DB0–

DB9 (DB11)

CS

CONVST

RD

BUSY

0V TO

REF IN

*RECOMMENDED REF IN VOLTAGE

Figure 5. Typical Connection Diagram

CAPACITIVE

DAC

VIN

AGND

A

SW1 B

2k⍀

SW2

CONTROL LOGIC

COMPARATOR

Figure 4. ADC Conversion Phase

–8–

REV. A

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