NJG1522KB2 データシートの表示（PDF） - Japan Radio Corporation

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NJG1522KB2

SPDT SWITCH GaAs MMIC

Japan Radio Corporation  

nTERMINAL INFORMATION

NJG1522KB2

No.

SYMBOL

DESCRIPTIONS

1

P1

RF port. This port is connected with PC port by controlling 6th pin (VCTL (H))

to 2.5~6.5V and 4th pin(VCTL(L)) to -0.2~+0.2V. An external capacitor is

required to block the DC bias voltage of internal circuit. (50~100MHz:

0.01uF, 0.1~0.5GHz: 1000pF, 0.5~2.5GHz: 56pF)

2

GND

3

P2

Ground terminal. Please connect this terminal with ground plane as close

as possible for excellent RF performance.

RF port. This port is connected with PC port by controlling 4th pin(VCTL(H))

to 2.5 – 6.5V and 6th pin(VCTL(L)) to -0.2~+0.2V. An external capacitor is

required to block the DC bias voltage of internal circuit. (50~100MHz:

0.01uF, 0.1~0.5GHz: 1000pF, 0.5~2.5GHz: 56pF)

Control port 2. The voltage of this port controls PC to P2 state. The ‘ON’

4

VCTL2

and ‘OFF’ state is toggled by controlling voltage of this terminal such as

high-state (2.5~6.5V) or low-state (-0.2~+0.2V). The voltage of 6th pin

have to be set to opposite state. The bypass capacitor has to be chosen

to reduce switching time delay from 10pF~1000pF range.

Common RF port. In order to block the DC bias voltage of internal circuit,

5

PC

an external capacitor is required. (50~100MHz: 0.01uF, 0.1~0.5GHz:

1000pF, 0.5~2.5GHz: 56pF)

Control port 1. The voltage of this port controls PC to P2 state. The ‘ON’

6

VCTL1

and ‘OFF’ state is toggled by controlling voltage of this terminal such as

high-state (2.5~6.5V) or low-state (-0.2~+0.2V). The voltage of 4th pin

have to be set to opposite state. The bypass capacitor has to be chosen

to reduce switching time delay from 10pF~1000pF range.

-3-

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